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    Memory transistor and memory unit with asymmetrical pocket doping region
    1.
    发明申请
    Memory transistor and memory unit with asymmetrical pocket doping region 有权
    存储晶体管和具有不对称口袋掺杂区域的存储单元

    公开(公告)号：US20070080390A1

    公开(公告)日：2007-04-12

    申请号：US11431265

    申请日：2006-05-10

    申请人： Christian Geissler ,  Franz Schuler ,  Danny Shum

    发明人： Christian Geissler ,  Franz Schuler ,  Danny Shum

    IPC分类号： H01L29/788

    CPC分类号： G11C16/0416

    摘要： An integrated memory transistor and a memory unit including a plurality of integrated memory transistors is disclosed. Generally, the integrated memory transistor includes an electron source, a channel region, a control region, a charge storage region, a source-side pocket doping region, and a drain-side pocket doping region. The electron source is operable to transport electrons to the channel region when the integrated memory transistor operates in a read mode. Further, the electron source includes a drain terminal region and a source terminal region. The channel region is arranged between the drain terminal region and source terminal region. The charge storage region is arranged between the control region and the channel region. The source-side doping region is arranged nearer to the source terminal region than to the drain terminal region. The drain-side pocket doping region is arranged asymmetrical to the source-side pocket doping region.

    摘要翻译： 公开了一种集成存储晶体管和包括多个集成存储晶体管的存储单元。 通常，集成存储晶体管包括电子源，沟道区，控制区，电荷存储区，源极侧掺杂区和漏极侧杂质掺杂区。 当集成存储晶体管以读取模式工作时，电子源可操作以将电子传输到沟道区域。 此外，电子源包括漏极端子区域和源极端子区域。 沟道区域布置在漏极端子区域和源极端子区域之间。 电荷存储区域设置在控制区域和沟道区域之间。 源极侧掺杂区域比漏极端子区域更靠近源极端子区域。 漏极侧杂质掺杂区域与源极侧掺杂区域不对称地布置。

    Memory transistor and memory unit with asymmetrical pocket doping region
    2.
    发明授权
    Memory transistor and memory unit with asymmetrical pocket doping region 有权
    存储晶体管和具有不对称口袋掺杂区域的存储单元

    公开(公告)号：US07433232B2

    公开(公告)日：2008-10-07

    申请号：US11431265

    申请日：2006-05-10

    申请人： Christian Geissler ,  Franz Schuler ,  Danny Pak-Chum Shum

    发明人： Christian Geissler ,  Franz Schuler ,  Danny Pak-Chum Shum

    IPC分类号： G11C16/04

    CPC分类号： G11C16/0416

    摘要： An integrated memory transistor and a memory unit including a plurality of integrated memory transistors is disclosed. Generally, the integrated memory transistor includes an electron source, a channel region, a control region, a charge storage region, a source-side pocket doping region, and a drain-side pocket doping region. The electron source is operable to transport electrons to the channel region when the integrated memory transistor operates in a read mode. Further, the electron source includes a drain terminal region and a source terminal region. The channel region is arranged between the drain terminal region and source terminal region. The charge storage region is arranged between the control region and the channel region. The source-side doping region is arranged nearer to the source terminal region than to the drain terminal region. The drain-side pocket doping region is arranged asymmetrical to the source-side pocket doping region.

    摘要翻译： 公开了一种集成存储晶体管和包括多个集成存储晶体管的存储单元。 通常，集成存储晶体管包括电子源，沟道区，控制区，电荷存储区，源极侧掺杂区和漏极侧杂质掺杂区。 当集成存储晶体管以读取模式工作时，电子源可操作以将电子传输到沟道区域。 此外，电子源包括漏极端子区域和源极端子区域。 沟道区域设置在漏极端子区域和源极端子区域之间。 电荷存储区域设置在控制区域和沟道区域之间。 源极侧掺杂区域比漏极端子区域更靠近源极端子区域。 漏极侧杂质掺杂区域与源极侧掺杂区域不对称地布置。

    Bit line structure and method for the production thereof
    3.
    发明授权
    Bit line structure and method for the production thereof 有权
    位线结构及其制造方法

    公开(公告)号：US08193059B2

    公开(公告)日：2012-06-05

    申请号：US12695277

    申请日：2010-01-28

    申请人： Ronald Kakoschke ,  Franz Schuler ,  Georg Tempel

    发明人： Ronald Kakoschke ,  Franz Schuler ,  Georg Tempel

    IPC分类号： H01L21/336

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/11521

    摘要： A bit line structure and associated fabrication method are provided for a semiconductor element or circuit arrangement. The bit line structure contains a surface bit line and a buried bit line. The buried bit line is formed in an upper section of a trench and is connected to an associated first doping region via a first connection layer. A first trench filling layer, which is insulated from the buried bit line by a second trench insulating layer, is situated in a lower section of the trench.

    摘要翻译： 为半导体元件或电路布置提供了位线结构和相关联的制造方法。 位线结构包含表面位线和掩埋位线。 掩埋位线形成在沟槽的上部，并且经由第一连接层连接到相关联的第一掺杂区域。 通过第二沟槽绝缘层与掩埋位线绝缘的第一沟槽填充层位于沟槽的下部。

    Nonvolatile memory element and production method thereof and storage memory arrangement
    4.
    发明授权
    Nonvolatile memory element and production method thereof and storage memory arrangement 有权
    非易失性存储元件及其制造方法和存储存储器装置

    公开(公告)号：US07923342B2

    公开(公告)日：2011-04-12

    申请号：US12040489

    申请日：2008-02-29

    申请人： Laurent Breuil ,  Franz Schuler ,  Georg Tempel

    发明人： Laurent Breuil ,  Franz Schuler ,  Georg Tempel

    IPC分类号： H01L21/20

    CPC分类号： H01L45/1608 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/33 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/148 ,  H01L45/149 ,  H01L45/16

    摘要： A nonvolatile memory element and associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying a field strength of an electric field generated by a second electrode in a changeover material. The field amplifier structure is a projection of the electrodes which projects into the changeover material. The memory element arrangement has multiple nonvolatile memory elements which are arranged in matrix form and can be addressed via bit lines arranged in column form and word lines arranged in row form.

    摘要翻译： 提出了一种非易失性存储元件和相关联的制造方法和存储元件布置。 非易失性存储元件具有切换材料和存在于切换材料上的第一和第二导电电极。 为了降低成形电压，第一电极具有用于放大由转换材料中的第二电极产生的电场的场强的场放大器结构。 场放大器结构是投影到切换材料中的电极的投影。 存储元件布置具有多个以矩阵形式布置的非易失性存储器元件，并且可以通过以列形式布置的位线和以行形式布置的字线来寻址。

    INTEGRATED CIRCUIT ARRANGEMENT COMPRISING ISOLATING TRENCHES AND A FIELD EFFECT TRANSISTOR AND ASSOCIATED PRODUCTION METHOD
    5.
    发明申请
    INTEGRATED CIRCUIT ARRANGEMENT COMPRISING ISOLATING TRENCHES AND A FIELD EFFECT TRANSISTOR AND ASSOCIATED PRODUCTION METHOD 有权
    集成电路布置包含隔离电容和场效应晶体管及相关生产方法

    公开(公告)号：US20110053341A1

    公开(公告)日：2011-03-03

    申请号：US12941527

    申请日：2010-11-08

    申请人： Ronald Kakoschke ,  Franz Schuler

    发明人： Ronald Kakoschke ,  Franz Schuler

    IPC分类号： H01L21/762

    CPC分类号： H01L27/11521 ,  H01L27/115 ,  H01L29/66825

    摘要： A memory circuit arrangement and a fabrication method are disclosed. The memory circuit arrangement has a memory cell area. The memory cell area contains memory cell transistors, one column of which are selected using a triple gate area selection transistor. The transistor has gate area that extends into isolating trenches. The isolating trenches isolate the memory cell in different columns of the memory cell array.

    摘要翻译： 公开了一种存储器电路装置和制造方法。 存储器电路装置具有存储单元区域。 存储单元区域包含存储单元晶体管，其一列使用三栅极区域选择晶体管来选择。 晶体管具有延伸到隔离沟槽中的栅极区域。 隔离沟槽将存储单元阵列的不同列中的存储单元隔离开。

    Non-volatile memory element and production method thereof and storage memory arrangement
    6.
    发明授权
    Non-volatile memory element and production method thereof and storage memory arrangement 有权
    非易失性存储元件及其制造方法和存储存储器装置

    公开(公告)号：US07361924B2

    公开(公告)日：2008-04-22

    申请号：US10522386

    申请日：2003-07-19

    申请人： Laurent Breuil ,  Franz Schuler ,  Georg Tempel

    发明人： Laurent Breuil ,  Franz Schuler ,  Georg Tempel

    IPC分类号： H01L47/00

    CPC分类号： H01L45/1608 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/33 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/148 ,  H01L45/149 ,  H01L45/16

    摘要： A nonvolatile memory element and associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying a field strength of an electric field generated by a second electrode in a changeover material. The field amplifier structure is a projection of the electrodes which projects into the changeover material. The memory element arrangement has multiple nonvolatile memory elements which are arranged in matrix form and can be addressed via bit lines arranged in column form and word lines arranged in row form.

    摘要翻译： 提出了一种非易失性存储元件和相关联的制造方法和存储元件布置。 非易失性存储元件具有切换材料和存在于切换材料上的第一和第二导电电极。 为了降低成形电压，第一电极具有用于放大由转换材料中的第二电极产生的电场的场强的场放大器结构。 场放大器结构是投影到切换材料中的电极的投影。 存储元件布置具有多个以矩阵形式布置的非易失性存储器元件，并且可以通过以列形式布置的位线和以行形式布置的字线来寻址。

    Bit line structure and production method thereof
    8.
    发明授权
    Bit line structure and production method thereof 有权
    位线结构及其制造方法

    公开(公告)号：US07262456B2

    公开(公告)日：2007-08-28

    申请号：US11273668

    申请日：2005-11-14

    申请人： Ronald Kakoschke ,  Franz Schuler ,  Georg Tempel

    发明人： Ronald Kakoschke ,  Franz Schuler ,  Georg Tempel

    IPC分类号： H01L27/788 ,  H01L21/366

    CPC分类号： H01L27/11568 ,  H01L27/115 ,  H01L27/11521

    摘要： The disclosure relates to a bit line structure and an associated production method for the bit line structure. In the bit line structure, at least in a region of a second contact and a plurality of first contact adjoining the latter, an isolation trench is filled with an electrically conductive trench filling layer. The isolation trench connects to the first doping regions adjoining the second contact for the purpose of realizing a buried contact bypass line.

    摘要翻译： 本公开涉及位线结构和相关联的位线结构的制造方法。 在位线结构中，至少在第二触点的区域和与其相邻的多个第一触点的区域中，隔离沟槽填充有导电沟槽填充层。 隔离沟槽连接到与第二接触相邻的第一掺杂区域，以实现埋地接触旁路线路。

    Nonvolatile memory element and production method thereof and storage memory arrangement
    10.
    发明授权
    Nonvolatile memory element and production method thereof and storage memory arrangement 有权
    非易失性存储元件及其制造方法和存储存储器装置

    公开(公告)号：US08377791B2

    公开(公告)日：2013-02-19

    申请号：US13043129

    申请日：2011-03-08

    申请人： Laurent Breuil ,  Franz Schuler ,  Georg Tempel

    发明人： Laurent Breuil ,  Franz Schuler ,  Georg Tempel

    IPC分类号： H01L21/20

    CPC分类号： H01L45/1608 ,  G11C13/0011 ,  G11C13/0069 ,  G11C2013/009 ,  G11C2213/15 ,  G11C2213/33 ,  G11C2213/72 ,  G11C2213/79 ,  H01L27/2409 ,  H01L27/2436 ,  H01L45/04 ,  H01L45/085 ,  H01L45/1233 ,  H01L45/1273 ,  H01L45/148 ,  H01L45/149 ,  H01L45/16

    摘要： A nonvolatile memory element and associated production methods and memory element arrangements are presented. The nonvolatile memory element has a changeover material and a first and second electrically conductive electrode present at the changeover material. To reduce a forming voltage, a first electrode has a field amplifier structure for amplifying a field strength of an electric field generated by a second electrode in a changeover material. The field amplifier structure is a projection of the electrodes which projects into the changeover material. The memory element arrangement has multiple nonvolatile memory elements which are arranged in matrix form and can be addressed via bit lines arranged in column form and word lines arranged in row form.

    摘要翻译： 提出了一种非易失性存储元件和相关联的制造方法和存储元件布置。 非易失性存储元件具有切换材料和存在于切换材料上的第一和第二导电电极。 为了降低成形电压，第一电极具有用于放大由转换材料中的第二电极产生的电场的场强的场放大器结构。 场放大器结构是投影到切换材料中的电极的投影。 存储元件布置具有多个以矩阵形式布置的非易失性存储器元件，并且可以通过以列形式布置的位线和以行形式布置的字线来寻址。