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    MULTILANE SERDES CLOCK AND DATA SKEW ALIGNMENT FOR MULTI-STANDARD SUPPORT
    1.
    发明申请
    MULTILANE SERDES CLOCK AND DATA SKEW ALIGNMENT FOR MULTI-STANDARD SUPPORT 审中-公开
    MULTILANE SERDES时钟和数据轴对齐多标准支持

    公开(公告)号：US20150304098A1

    公开(公告)日：2015-10-22

    申请号：US14755127

    申请日：2015-06-30

    Applicant: Broadcom Corporation

    Inventor： Adesh Garg ,  Jun Cao ,  Namik Kocaman ,  Kuo-J (Nick) Huang ,  Delong Cui ,  Afshin Momtaz

    IPC: H04L7/00

    CPC classification number: H04L7/0025 ,  G06F1/10 ,  G06F1/3203 ,  H04L7/033 ,  H04L25/14

    Abstract: A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.

    Abstract translation: 通信系统可以包括根据一个或多个通信标准操作的多个通信信道。 通道可以从一个或多个主时钟信号产生数据时钟。 可以使用相位检测器对数据时钟的相位进行校准，以确定各个相位关系，并使用相位内插器来调整各个时钟相位。 通信系统可以包括在不同数据时钟频率下操作的通信信道。 这些系统可以对它们各自的数据时钟进行分频，以实现用于其相位对准的公共时钟频率。 可以禁用相位检测器和相关电路，以在不使用时节省电力。

    Multilane SERDES clock and data skew alignment for multi-standard support
    3.
    发明授权
    Multilane SERDES clock and data skew alignment for multi-standard support 有权
    多晶硅SERDES时钟和数据偏移对齐，适用于多标准支持

    公开(公告)号：US09100167B2

    公开(公告)日：2015-08-04

    申请号：US13691482

    申请日：2012-11-30

    Applicant: Broadcom Corporation

    Inventor： Adesh Garg ,  Jun Cao ,  Namik Kocaman ,  Kuo-J Huang ,  Delong Cui ,  Afshin Momtaz

    IPC: G06F1/04 ,  H04L7/033 ,  G06F1/10 ,  H04L25/14 ,  H04L7/00

    CPC classification number: H04L7/0025 ,  G06F1/10 ,  G06F1/3203 ,  H04L7/033 ,  H04L25/14

    Abstract: A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.

    Abstract translation: 通信系统可以包括根据一个或多个通信标准操作的多个通信信道。 通道可以从一个或多个主时钟信号产生数据时钟。 可以使用相位检测器对数据时钟的相位进行校准，以确定各个相位关系，并使用相位内插器来调整各个时钟相位。 通信系统可以包括在不同数据时钟频率下操作的通信信道。 这些系统可以对它们各自的数据时钟进行分频，以实现用于其相位对准的公共时钟频率。 可以禁用相位检测器和相关电路，以在不使用时节省电力。

    Method and apparatus for reference-less repeater with digital control
    4.
    发明授权
    Method and apparatus for reference-less repeater with digital control 有权
    具有数字控制功能的无参考中继器的方法和装置

    公开(公告)号：US09077328B1

    公开(公告)日：2015-07-07

    申请号：US14246836

    申请日：2014-04-07

    Applicant: Broadcom Corporation

    Inventor： Magesh Valliappan ,  Afshin Momtaz ,  Namik Kocaman ,  Vasudevan Parthasarathy

    IPC: H04L27/06 ,  H03K5/26 ,  H04L7/033 ,  H04B7/155

    CPC classification number: H03K5/26 ,  H04B7/155 ,  H04L7/033

    Abstract: Reference-less repeating circuits provide significant advantages over repeating circuits requiring external frequency references. These repeating circuits eliminate the need for external frequency references provide significant power, layout, and physical isolation advantages. Digitally controlled reference-less repeating circuits have a relatively narrow frequency detection range, but typically consume significantly less power than analog repeating circuits while providing data rate flexibility, particularly at lower data rates. Due to the narrow frequency detection range of digitally controlled reference-less repeating circuits, efficient frequency estimation techniques allow these circuits to quickly lock to an input signal, and provide an accurate repeated output signal.

    Abstract translation: 无需外部频率参考的无需重复电路可提供超过重复电路的显着优点。 这些重复电路消除了对外部频率参考的需求，提供了显着的功率，布局和物理隔离优势。 数字控制的无参考中继电路具有相对较窄的频率检测范围，但是通常比模拟重复电路消耗明显更少的功率，同时提供数据速率灵活性，特别是在较低的数据速率下。 由于数字控制的无参考中继电路的窄频率检测范围，有效的频率估计技术允许这些电路快速锁定到输入信号，并提供准确的重复输出信号。

    Quasi-digital receiver for high speed SER-DES
    5.
    发明授权
    Quasi-digital receiver for high speed SER-DES 有权
    用于高速SER-DES的准数字接收机

    公开(公告)号：US08958501B2

    公开(公告)日：2015-02-17

    申请号：US13720623

    申请日：2012-12-19

    Applicant: Broadcom Corporation

    Inventor： Ali Nazemi ,  Mahmoud Reza Ahmadi ,  Tamer Ali ,  Bo Zhang ,  Mohammed Abdul-Latif ,  Namik Kocaman ,  Afshin Momtaz

    IPC: H03K9/00 ,  H04L7/00 ,  H04L25/02 ,  H04L25/06

    CPC classification number: H04L7/00 ,  H04L7/002 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/0296 ,  H04L25/06

    Abstract: Techniques are described herein that provide an interface for receiving and deserializing digital bit stream(s). For instance, a receiver for a high-speed deserializer may include digital slicers, a digital phase interpolator, and a digital clock phase generator. The digital slicers may be configured to determine a digital value of a data input. The digital phase interpolator may be configured to generate an interpolated clock signal based on input clock signals that correspond to respective phases of a reference clock. The phase of the interpolated clock tracks the data input to the receiver through a clock recovery loop. The digital clock phase generator may be configured to generate output clock signals to control timing of the respective digital slicers. The receiver may further include a single digital eye monitor configured to monitor a data eye of the data input.

    Abstract translation: 这里描述了提供用于接收和反序列化数字比特流的接口的技术。 例如，用于高速解串器的接收器可以包括数字限幅器，数字相位内插器和数字时钟相位发生器。 数字限幅器可以被配置为确定数据输入的数字值。 数字相位插值器可以被配置为基于对应于参考时钟的各个相位的输入时钟信号来产生内插时钟信号。 内插时钟的相位通过时钟恢复循环跟踪输入到接收器的数据。 数字时钟相位发生器可以被配置为产生输出时钟信号以控制各个数字限幅器的定时。 接收器还可以包括被配置为监视数据输入的数据眼睛的单个数字眼睛监视器。

    MULTILANE SERDES CLOCK AND DATA SKEW ALIGNMENT FOR MULTI-STANDARD SUPPORT
    6.
    发明申请
    MULTILANE SERDES CLOCK AND DATA SKEW ALIGNMENT FOR MULTI-STANDARD SUPPORT 有权
    MULTILANE SERDES时钟和数据轴对齐多标准支持

    公开(公告)号：US20140153680A1

    公开(公告)日：2014-06-05

    申请号：US13691482

    申请日：2012-11-30

    Applicant: BROADCOM CORPORATION

    Inventor： Adesh Garg ,  Jun Cao ,  Namik Kocaman ,  Kuo-J Huang ,  Delong Cui ,  Afshin Momtaz

    IPC: H04L7/033

    CPC classification number: H04L7/0025 ,  G06F1/10 ,  G06F1/3203 ,  H04L7/033 ,  H04L25/14

    Abstract: A communication system may include a number of communication channels operating in accordance with one or more communication standards. The channels may generate data clocks from one or more master clock signals. The phase of the data clocks may be aligned using phase detectors for determining respective phase relationships and using phase interpolators for adjusting respective clock phases. The communication system may include communication channels that operate at different data clock frequencies. These systems may divide their respective data clocks in order to achieve a common clock frequency for use in their phase alignment. The phase detectors and associated circuitry may be disabled to save power when not in use.

    Abstract translation: 通信系统可以包括根据一个或多个通信标准操作的多个通信信道。 通道可以从一个或多个主时钟信号产生数据时钟。 可以使用相位检测器对数据时钟的相位进行校准，以确定各个相位关系，并使用相位内插器来调整各个时钟相位。 通信系统可以包括在不同数据时钟频率下操作的通信信道。 这些系统可以对它们各自的数据时钟进行分频，以实现用于其相位对准的公共时钟频率。 可以禁用相位检测器和相关电路，以在不使用时节省电力。

    QUASI-DIGITAL RECEIVER FOR HIGH SPEED SER-DES
    8.
    发明申请
    QUASI-DIGITAL RECEIVER FOR HIGH SPEED SER-DES 有权
    QUASI-DIGITAL接收器用于高速伺服系统

    公开(公告)号：US20140146922A1

    公开(公告)日：2014-05-29

    申请号：US13720623

    申请日：2012-12-19

    Applicant: BROADCOM CORPORATION

    Inventor： Ali Nazemi ,  Mahmoud Reza Ahmadi ,  Tamer Ali ,  Bo Zhang ,  Mohammed Abdul-Latif ,  Namik Kocaman ,  Afshin Momtaz

    IPC: H04L25/02

    CPC classification number: H04L7/00 ,  H04L7/002 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/0296 ,  H04L25/06

    Abstract: Techniques are described herein that provide an interface for receiving and deserializing digital bit stream(s). For instance, a receiver for a high-speed deserializer may include digital slicers, a digital phase interpolator, and a digital clock phase generator. The digital slicers may be configured to determine a digital value of a data input. The digital phase interpolator may be configured to generate an interpolated clock signal based on input clock signals that correspond to respective phases of a reference clock. The phase of the interpolated clock tracks the data input to the receiver through a clock recovery loop. The digital clock phase generator may be configured to generate output clock signals to control timing of the respective digital slicers. The receiver may further include a single digital eye monitor configured to monitor a data eye of the data input.

    Abstract translation: 这里描述了提供用于接收和反序列化数字比特流的接口的技术。 例如，用于高速解串器的接收器可以包括数字限幅器，数字相位内插器和数字时钟相位发生器。 数字限幅器可以被配置为确定数据输入的数字值。 数字相位插值器可以被配置为基于对应于参考时钟的各个相位的输入时钟信号来产生内插时钟信号。 内插时钟的相位通过时钟恢复循环跟踪输入到接收器的数据。 数字时钟相位发生器可以被配置为产生输出时钟信号以控制各个数字限幅器的定时。 接收器还可以包括被配置为监视数据输入的数据眼睛的单个数字眼睛监视器。

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