公开(公告)号：US20140146922A1

公开(公告)日：2014-05-29

申请号：US13720623

申请日：2012-12-19

Applicant: BROADCOM CORPORATION

Inventor： Ali Nazemi ,  Mahmoud Reza Ahmadi ,  Tamer Ali ,  Bo Zhang ,  Mohammed Abdul-Latif ,  Namik Kocaman ,  Afshin Momtaz

IPC: H04L25/02

CPC classification number: H04L7/00 ,  H04L7/002 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/0296 ,  H04L25/06

Abstract: Techniques are described herein that provide an interface for receiving and deserializing digital bit stream(s). For instance, a receiver for a high-speed deserializer may include digital slicers, a digital phase interpolator, and a digital clock phase generator. The digital slicers may be configured to determine a digital value of a data input. The digital phase interpolator may be configured to generate an interpolated clock signal based on input clock signals that correspond to respective phases of a reference clock. The phase of the interpolated clock tracks the data input to the receiver through a clock recovery loop. The digital clock phase generator may be configured to generate output clock signals to control timing of the respective digital slicers. The receiver may further include a single digital eye monitor configured to monitor a data eye of the data input.

Abstract translation: 这里描述了提供用于接收和反序列化数字比特流的接口的技术。 例如，用于高速解串器的接收器可以包括数字限幅器，数字相位内插器和数字时钟相位发生器。 数字限幅器可以被配置为确定数据输入的数字值。 数字相位插值器可以被配置为基于对应于参考时钟的各个相位的输入时钟信号来产生内插时钟信号。 内插时钟的相位通过时钟恢复循环跟踪输入到接收器的数据。 数字时钟相位发生器可以被配置为产生输出时钟信号以控制各个数字限幅器的定时。 接收器还可以包括被配置为监视数据输入的数据眼睛的单个数字眼睛监视器。

公开(公告)号：US09325316B1

公开(公告)日：2016-04-26

申请号：US14709368

申请日：2015-05-11

Applicant: BROADCOM CORPORATION

Inventor： Amr Amin Hafez Amin Abou-El-Sonoun ,  Ramy Awad ,  Mohammed Abdul-Latif ,  Adesh Garg ,  Henry Park ,  Anand Jitendra Vasani ,  Ullas Singh ,  Namik Kemal Kocaman ,  Afshin Momtaz

IPC: H03L5/02 ,  H03K19/0185

CPC classification number: H03K19/018514

Abstract: A low-power high-swing current-mode logic (CML) driver circuit includes a first differential-pair and a second differential-pair. The first differential-pair includes first transistors, and is coupled to a first voltage supply that supplies a first voltage. The second differential-pair includes second transistors, and a common node of the second differential-pair is coupled to a second voltage supply. The second voltage supply supplies a second voltage that is higher than the first voltage. Control terminals of the first transistors are coupled to control terminals of the second transistors to form input nodes of the driver circuit.

Abstract translation: 低功率高频摆动电流模式逻辑（CML）驱动电路包括第一差分对和第二差分对。 第一差分对包括第一晶体管，并且耦合到提供第一电压的第一电压源。 第二差分对包括第二晶体管，并且第二差分对的公共节点耦合到第二电压源。 第二电压源提供高于第一电压的第二电压。 第一晶体管的控制端子耦合到第二晶体管的控制端，以形成驱动器电路的输入节点。

公开(公告)号：US08958501B2

公开(公告)日：2015-02-17

申请号：US13720623

申请日：2012-12-19

Applicant: Broadcom Corporation

Inventor： Ali Nazemi ,  Mahmoud Reza Ahmadi ,  Tamer Ali ,  Bo Zhang ,  Mohammed Abdul-Latif ,  Namik Kocaman ,  Afshin Momtaz

IPC: H03K9/00 ,  H04L7/00 ,  H04L25/02 ,  H04L25/06

CPC classification number: H04L7/00 ,  H04L7/002 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/0296 ,  H04L25/06

Abstract: Techniques are described herein that provide an interface for receiving and deserializing digital bit stream(s). For instance, a receiver for a high-speed deserializer may include digital slicers, a digital phase interpolator, and a digital clock phase generator. The digital slicers may be configured to determine a digital value of a data input. The digital phase interpolator may be configured to generate an interpolated clock signal based on input clock signals that correspond to respective phases of a reference clock. The phase of the interpolated clock tracks the data input to the receiver through a clock recovery loop. The digital clock phase generator may be configured to generate output clock signals to control timing of the respective digital slicers. The receiver may further include a single digital eye monitor configured to monitor a data eye of the data input.

Abstract translation: 这里描述了提供用于接收和反序列化数字比特流的接口的技术。 例如，用于高速解串器的接收器可以包括数字限幅器，数字相位内插器和数字时钟相位发生器。 数字限幅器可以被配置为确定数据输入的数字值。 数字相位插值器可以被配置为基于对应于参考时钟的各个相位的输入时钟信号来产生内插时钟信号。 内插时钟的相位通过时钟恢复循环跟踪输入到接收器的数据。 数字时钟相位发生器可以被配置为产生输出时钟信号以控制各个数字限幅器的定时。 接收器还可以包括被配置为监视数据输入的数据眼睛的单个数字眼睛监视器。