公开(公告)号：US20160182080A1

公开(公告)日：2016-06-23

申请号：US14616566

申请日：2015-02-06

Applicant: BROADCOM CORPORATION

Inventor： Anand Jitendra Vasani ,  Ali Nazemi ,  Jun Cao ,  Afshin Momtaz

IPC: H03M1/68 ,  H03M1/10 ,  H03M1/74 ,  H03M1/00

CPC classification number: H03M1/68 ,  H03M1/002 ,  H03M1/068 ,  H03M1/1028 ,  H03M1/1047 ,  H03M1/74 ,  H03M1/80

Abstract: A low-power reconfigurable voltage-mode digital-to-analog converter (DAC) driver circuit includes a first and a second supply voltage and a number of DAC units. Each DAC unit is coupled to a respective bit of a digital input. The DAC units are configured to maintain a constant output impedance. Each DAC unit includes one or more complementary switch pairs that couple first nodes of one or more respective impedances to one of the first or the second supply voltage, based on the respective bit of the digital input. Second nodes of the one or more respective impedances are coupled to an output node.

Abstract translation: 低功率可重构电压模式数模转换器（DAC）驱动电路包括第一和第二电源电压以及多个DAC单元。 每个DAC单元耦合到数字输入的相应位。 DAC单元配置为保持恒定的输出阻抗。 每个DAC单元包括一个或多个互补开关对，其基于数字输入的相应位将一个或多个相应阻抗的第一节点耦合到第一或第二电源电压中的一个。 一个或多个相应阻抗的第二节点耦合到输出节点。

公开(公告)号：US09413381B2

公开(公告)日：2016-08-09

申请号：US14616566

申请日：2015-02-06

Applicant: BROADCOM CORPORATION

Inventor： Anand Jitendra Vasani ,  Ali Nazemi ,  Jun Cao ,  Afshin Momtaz

IPC: H03M1/66 ,  H03M1/68 ,  H03M1/00 ,  H03M1/10 ,  H03M1/74

CPC classification number: H03M1/68 ,  H03M1/002 ,  H03M1/068 ,  H03M1/1028 ,  H03M1/1047 ,  H03M1/74 ,  H03M1/80

Abstract: A low-power reconfigurable voltage-mode digital-to-analog converter (DAC) driver circuit includes a first and a second supply voltage and a number of DAC units. Each DAC unit is coupled to a respective bit of a digital input. The DAC units are configured to maintain a constant output impedance. Each DAC unit includes one or more complementary switch pairs that couple first nodes of one or more respective impedances to one of the first or the second supply voltage, based on the respective bit of the digital input. Second nodes of the one or more respective impedances are coupled to an output node.

Abstract translation: 低功率可重构电压模式数模转换器（DAC）驱动电路包括第一和第二电源电压以及多个DAC单元。 每个DAC单元耦合到数字输入的相应位。 DAC单元配置为保持恒定的输出阻抗。 每个DAC单元包括一个或多个互补开关对，其基于数字输入的相应位将一个或多个相应阻抗的第一节点耦合到第一或第二电源电压中的一个。 一个或多个相应阻抗的第二节点耦合到输出节点。

公开(公告)号：US09325316B1

公开(公告)日：2016-04-26

申请号：US14709368

申请日：2015-05-11

Applicant: BROADCOM CORPORATION

Inventor： Amr Amin Hafez Amin Abou-El-Sonoun ,  Ramy Awad ,  Mohammed Abdul-Latif ,  Adesh Garg ,  Henry Park ,  Anand Jitendra Vasani ,  Ullas Singh ,  Namik Kemal Kocaman ,  Afshin Momtaz

IPC: H03L5/02 ,  H03K19/0185

CPC classification number: H03K19/018514

Abstract: A low-power high-swing current-mode logic (CML) driver circuit includes a first differential-pair and a second differential-pair. The first differential-pair includes first transistors, and is coupled to a first voltage supply that supplies a first voltage. The second differential-pair includes second transistors, and a common node of the second differential-pair is coupled to a second voltage supply. The second voltage supply supplies a second voltage that is higher than the first voltage. Control terminals of the first transistors are coupled to control terminals of the second transistors to form input nodes of the driver circuit.

Abstract translation: 低功率高频摆动电流模式逻辑（CML）驱动电路包括第一差分对和第二差分对。 第一差分对包括第一晶体管，并且耦合到提供第一电压的第一电压源。 第二差分对包括第二晶体管，并且第二差分对的公共节点耦合到第二电压源。 第二电压源提供高于第一电压的第二电压。 第一晶体管的控制端子耦合到第二晶体管的控制端，以形成驱动器电路的输入节点。