公开(公告)号：US20150092829A1

公开(公告)日：2015-04-02

申请号：US14072641

申请日：2013-11-05

Applicant: Broadcom Corporation

Inventor： Tamer ALI ,  Hassan Maarefi ,  Mahmoud Reza Ahmadi ,  Afshin Momtaz

IPC: H04L25/03

CPC classification number: H04L25/03019 ,  H04L25/0288 ,  H04L25/03885 ,  H04L2025/03471 ,  H04L2025/03681

Abstract: A device for passive equalization and slew-rate control of a signal includes a first branch that includes a first driver coupled in series with an equalization capacitor, and a second branch that includes a second driver coupled in series with a resistor. The second branch may be coupled in parallel to the first branch, and the first branch may be configurable to enable one of passive equalization or slew-rate control of the signal based on a mode control signal.

Abstract translation: 用于信号的无源均衡和转换速率控制的装置包括第一分支，其包括与均衡电容器串联耦合的第一驱动器，以及包括与电阻器串联耦合的第二驱动器的第二分支。 第二分支可以与第一分支并联耦合，并且第一分支可以被配置为基于模式控制信号使能信号的无源均衡或转换速率控制之一。

公开(公告)号：US09246670B2

公开(公告)日：2016-01-26

申请号：US14637306

申请日：2015-03-03

Applicant: BROADCOM CORPORATION

Inventor： Mahmoud Reza Ahmadi ,  Siavash Fallahi ,  Tamer Ali ,  Ali Nazemi ,  Hassan Maarefi ,  Burak Catli ,  Afshin Momtaz

IPC: H04L7/033 ,  H03L7/00 ,  H03L7/099 ,  H04L7/00

CPC classification number: H04L7/0331 ,  H03L7/00 ,  H03L7/0996 ,  H04L7/0016

Abstract: A high-speed clock generator device includes a phase-interpolator (PI) circuit, a smoothing block, and inverter-based low-pass filters. The PI circuit receives a multiple clock signals with different phase angles and generates an output clock signal having a correct phase angle. The smoothing block smooths the clock signals with different phase angles and generates a number of smooth clock signals featuring improved linearity. The inverter-based low-pass filters filter harmonics of the clock signals with different phase angles.

Abstract translation: 高速时钟发生器装置包括相位插值器（PI）电路，平滑块和基于反相器的低通滤波器。 PI电路接收具有不同相位角的多个时钟信号，并产生具有正确相位角的输出时钟信号。 平滑块平滑具有不同相位角的时钟信号，并产生许多具有改进线性度的平滑时钟信号。 基于逆变器的低通滤波器滤波具有不同相位角的时钟信号的谐波。

公开(公告)号：US20140104086A1

公开(公告)日：2014-04-17

申请号：US13754374

申请日：2013-01-30

Applicant: BROADCOM CORPORATION

Inventor： Bo Zhang ,  Ali Nazemi ,  Mahmoud Reza Ahmadi ,  Afshin Momtaz ,  Heng Zhang ,  Hassan Maarefi

IPC: H03M1/10 ,  H03M1/36

CPC classification number: H03M1/1009 ,  H03M1/069 ,  H03M1/1023 ,  H03M1/141 ,  H03M1/188 ,  H03M1/361

Abstract: Methods and apparatuses are described for a DSP receiver with an analog-to-digital converter (ADC) having high speed, low BER performance with low power and area requirements. Speed is increased for multi-path ADC configurations by resolving a conventional bottleneck. ADC performance is improved by integrating calibration and error detection and correction, such as distributed offset calibration and redundant comparators. Power and area requirements are dramatically reduced by using low BER rectification to nearly halve the number of comparators in a conventional high speed, low BER flash ADC.

Abstract translation: 描述了具有模数转换器（ADC）的DSP接收机的方法和装置，具有高速度，低BER性能，低功率和面积要求。 通过解决传统的瓶颈，提高了多路径ADC配置的速度。 通过集成校准和错误检测和校正（例如分布式偏移校准和冗余比较器）来提高ADC性能。 通过使用低BER整流将传统高速，低BER闪存ADC中的比较器数量减半，功率和面积要求大大降低。

公开(公告)号：US20140146922A1

公开(公告)日：2014-05-29

申请号：US13720623

申请日：2012-12-19

Applicant: BROADCOM CORPORATION

Inventor： Ali Nazemi ,  Mahmoud Reza Ahmadi ,  Tamer Ali ,  Bo Zhang ,  Mohammed Abdul-Latif ,  Namik Kocaman ,  Afshin Momtaz

IPC: H04L25/02

CPC classification number: H04L7/00 ,  H04L7/002 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/0296 ,  H04L25/06

Abstract: Techniques are described herein that provide an interface for receiving and deserializing digital bit stream(s). For instance, a receiver for a high-speed deserializer may include digital slicers, a digital phase interpolator, and a digital clock phase generator. The digital slicers may be configured to determine a digital value of a data input. The digital phase interpolator may be configured to generate an interpolated clock signal based on input clock signals that correspond to respective phases of a reference clock. The phase of the interpolated clock tracks the data input to the receiver through a clock recovery loop. The digital clock phase generator may be configured to generate output clock signals to control timing of the respective digital slicers. The receiver may further include a single digital eye monitor configured to monitor a data eye of the data input.

Abstract translation: 这里描述了提供用于接收和反序列化数字比特流的接口的技术。 例如，用于高速解串器的接收器可以包括数字限幅器，数字相位内插器和数字时钟相位发生器。 数字限幅器可以被配置为确定数据输入的数字值。 数字相位插值器可以被配置为基于对应于参考时钟的各个相位的输入时钟信号来产生内插时钟信号。 内插时钟的相位通过时钟恢复循环跟踪输入到接收器的数据。 数字时钟相位发生器可以被配置为产生输出时钟信号以控制各个数字限幅器的定时。 接收器还可以包括被配置为监视数据输入的数据眼睛的单个数字眼睛监视器。

公开(公告)号：US09001869B2

公开(公告)日：2015-04-07

申请号：US13946981

申请日：2013-07-19

Applicant: Broadcom Corporation

Inventor： Mahmoud Reza Ahmadi ,  Siavash Fallahi ,  Tamer Ali ,  Ali Nazemi ,  Hassan Maarefi ,  Burak Catli ,  Afshin Momtaz

IPC: H04B3/36 ,  H03L7/00

CPC classification number: H04L7/0331 ,  H03L7/00 ,  H03L7/0996 ,  H04L7/0016

Abstract: A device for high-speed clock generation may include an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate multiple clock signals with different equally spaced phase angles. A phase-interpolator (PI) circuit may be configured to receive the multiple coarse spaced clock signals and to generate an output clock signal having a correct phase angle. The PI circuit may include a smoothing block that may be configured to smooth the multiple clock signals with different phase angles and to generate multiple smooth clock signals. A pulling block may be configured to pull edges of the multiple smooth clock signals closer to one another.

Abstract translation: 用于高速时钟产生的装置可以包括被配置为接收一个或多个输入时钟信号并且生成具有不同等间隔的相位角的多个时钟信号的注入锁定环形振荡器（ILRO）。 相位插值器（PI）电路可以被配置为接收多个粗略间隔的时钟信号并且产生具有正确相位角的输出时钟信号。 PI电路可以包括平滑块，其可以被配置为平滑具有不同相位角的多个时钟信号并且生成多个平滑时钟信号。 牵引块可以被配置成拉近多个平滑时钟信号的边缘彼此更接近。

公开(公告)号：US08836553B2

公开(公告)日：2014-09-16

申请号：US13754374

申请日：2013-01-30

Applicant: Broadcom Corporation

Inventor： Bo Zhang ,  Ali Nazemi ,  Mahmoud Reza Ahmadi ,  Afshin Momtaz ,  Heng Zhang ,  Hassan Maarefi

IPC: H03M1/10

CPC classification number: H03M1/1009 ,  H03M1/069 ,  H03M1/1023 ,  H03M1/141 ,  H03M1/188 ,  H03M1/361

Abstract: Methods and apparatuses are described for a DSP receiver with an analog-to-digital converter (ADC) having high speed, low BER performance with low power and area requirements. Speed is increased for multi-path ADC configurations by resolving a conventional bottleneck. ADC performance is improved by integrating calibration and error detection and correction, such as distributed offset calibration and redundant comparators. Power and area requirements are dramatically reduced by using low BER rectification to nearly halve the number of comparators in a conventional high speed, low BER flash ADC.

Abstract translation: 描述了具有模数转换器（ADC）的DSP接收机的方法和装置，具有高速度，低BER性能，低功率和面积要求。 通过解决传统的瓶颈，提高了多路径ADC配置的速度。 通过集成校准和错误检测和校正（例如分布式偏移校准和冗余比较器）来提高ADC性能。 通过使用低BER整流将传统高速，低BER闪存ADC中的比较器数量减半，功率和面积要求大大降低。

公开(公告)号：US20140241442A1

公开(公告)日：2014-08-28

申请号：US13946981

申请日：2013-07-19

Applicant: BROADCOM CORPORATION

Inventor： Mahmoud Reza Ahmadi ,  Siavash Fallahi ,  Tamer Ali ,  Ali Nazemi ,  Hassan Maarefi ,  Burak Catli ,  Afshin Momtaz

IPC: H03L7/00

CPC classification number: H04L7/0331 ,  H03L7/00 ,  H03L7/0996 ,  H04L7/0016

Abstract: A device for high-speed clock generation may include an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate multiple clock signals with different equally spaced phase angles. A phase-interpolator (PI) circuit may be configured to receive the multiple coarse spaced clock signals and to generate an output clock signal having a correct phase angle. The PI circuit may include a smoothing block that may be configured to smooth the multiple clock signals with different phase angles and to generate multiple smooth clock signals. A pulling block may be configured to pull edges of the multiple smooth clock signals closer to one another.

Abstract translation: 用于高速时钟产生的装置可以包括被配置为接收一个或多个输入时钟信号并且生成具有不同等间隔的相位角的多个时钟信号的注入锁定环形振荡器（ILRO）。 相位插值器（PI）电路可以被配置为接收多个粗略间隔的时钟信号并且产生具有正确相位角的输出时钟信号。 PI电路可以包括平滑块，其可以被配置为平滑具有不同相位角的多个时钟信号并且生成多个平滑时钟信号。 牵引块可以被配置成拉近多个平滑时钟信号的边缘彼此更接近。

公开(公告)号：US09024659B2

公开(公告)日：2015-05-05

申请号：US14072641

申请日：2013-11-05

Applicant: Broadcom Corporation

Inventor： Tamer Ali ,  Hassan Maarefi ,  Mahmoud Reza Ahmadi ,  Afshin Momtaz

IPC: H03K19/094 ,  H03K17/16 ,  H04L25/03

CPC classification number: H04L25/03019 ,  H04L25/0288 ,  H04L25/03885 ,  H04L2025/03471 ,  H04L2025/03681

Abstract: A device for passive equalization and slew-rate control of a signal includes a first branch and a second branch. The first branch includes a first driver coupled in series with an equalization capacitor. The second branch includes a second driver coupled in series with a resistor. The second branch may be coupled in parallel to the first branch. The first branch may be configurable to enable either passive equalization or slew-rate control of the signal based on a mode control signal.

Abstract translation: 用于信号的无源均衡和转换速率控制的装置包括第一分支和第二分支。 第一分支包括与均衡电容器串联耦合的第一驱动器。 第二分支包括与电阻器串联耦合的第二驱动器。 第二分支可以与第一分支并联耦合。 第一分支可以被配置为基于模式控制信号实现对信号的无源均衡或转换速率控制。

公开(公告)号：US08958501B2

公开(公告)日：2015-02-17

申请号：US13720623

申请日：2012-12-19

Applicant: Broadcom Corporation

Inventor： Ali Nazemi ,  Mahmoud Reza Ahmadi ,  Tamer Ali ,  Bo Zhang ,  Mohammed Abdul-Latif ,  Namik Kocaman ,  Afshin Momtaz

IPC: H03K9/00 ,  H04L7/00 ,  H04L25/02 ,  H04L25/06

CPC classification number: H04L7/00 ,  H04L7/002 ,  H04L25/0272 ,  H04L25/0292 ,  H04L25/0296 ,  H04L25/06

Abstract: Techniques are described herein that provide an interface for receiving and deserializing digital bit stream(s). For instance, a receiver for a high-speed deserializer may include digital slicers, a digital phase interpolator, and a digital clock phase generator. The digital slicers may be configured to determine a digital value of a data input. The digital phase interpolator may be configured to generate an interpolated clock signal based on input clock signals that correspond to respective phases of a reference clock. The phase of the interpolated clock tracks the data input to the receiver through a clock recovery loop. The digital clock phase generator may be configured to generate output clock signals to control timing of the respective digital slicers. The receiver may further include a single digital eye monitor configured to monitor a data eye of the data input.

Abstract translation: 这里描述了提供用于接收和反序列化数字比特流的接口的技术。 例如，用于高速解串器的接收器可以包括数字限幅器，数字相位内插器和数字时钟相位发生器。 数字限幅器可以被配置为确定数据输入的数字值。 数字相位插值器可以被配置为基于对应于参考时钟的各个相位的输入时钟信号来产生内插时钟信号。 内插时钟的相位通过时钟恢复循环跟踪输入到接收器的数据。 数字时钟相位发生器可以被配置为产生输出时钟信号以控制各个数字限幅器的定时。 接收器还可以包括被配置为监视数据输入的数据眼睛的单个数字眼睛监视器。