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1.发明授权Compact low-power fully digital CMOS clock generation apparatus for high-speed SerDes 有权紧凑型低功耗全数字CMOS时钟发生装置，用于高速SerDes公开(公告)号：US09246670B2
公开(公告)日：2016-01-26
申请号：US14637306
申请日：2015-03-03
Applicant: BROADCOM CORPORATION
Inventor： Mahmoud Reza Ahmadi , Siavash Fallahi , Tamer Ali , Ali Nazemi , Hassan Maarefi , Burak Catli , Afshin Momtaz
CPC classification number: H04L7/0331 , H03L7/00 , H03L7/0996 , H04L7/0016
Abstract: A high-speed clock generator device includes a phase-interpolator (PI) circuit, a smoothing block, and inverter-based low-pass filters. The PI circuit receives a multiple clock signals with different phase angles and generates an output clock signal having a correct phase angle. The smoothing block smooths the clock signals with different phase angles and generates a number of smooth clock signals featuring improved linearity. The inverter-based low-pass filters filter harmonics of the clock signals with different phase angles.
Abstract translation: 高速时钟发生器装置包括相位插值器（PI）电路，平滑块和基于反相器的低通滤波器。 PI电路接收具有不同相位角的多个时钟信号，并产生具有正确相位角的输出时钟信号。 平滑块平滑具有不同相位角的时钟信号，并产生许多具有改进线性度的平滑时钟信号。 基于逆变器的低通滤波器滤波具有不同相位角的时钟信号的谐波。
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公开(公告)号：US09344268B1
公开(公告)日：2016-05-17
申请号：US14668165
申请日：2015-03-25
Applicant: Broadcom Corporation
Inventor： Ali Nazemi , Burak Catli , Wayne Wah-Yuen Wong , Kangmin Hu , Hyo Gyuem Rhew , Delong Cui , Jun Cao , Bo Zhang , Afshin Doctor Momtaz
CPC classification number: H04J3/0685 , H04J3/047 , H04L7/0025
Abstract: A phase alignment architecture enhances the performance of communication systems. The architecture aligns a divided clock (e.g., in differential Inphase (I) and Quadrature (Q)) to a main clock, even at extremely high speeds, where skew variations of the divided clock are comparable to the main clock period. The improvement in phase alignment facilitates ultra high-speed communications.
Abstract translation: 相位对准架构增强了通信系统的性能。 即使在非常高的速度下，分频时钟的分频时钟（例如，差分同相（I）和正交（Q））与主时钟对准，其中分频时钟的偏移变化与主时钟周期相当。 相位对准的改进有助于超高速通信。
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3.发明授权Compact low-power fully digital CMOS clock generation apparatus for high-speed SerDes 有权紧凑型低功耗全数字CMOS时钟发生装置，用于高速SerDes公开(公告)号：US09001869B2
公开(公告)日：2015-04-07
申请号：US13946981
申请日：2013-07-19
Applicant: Broadcom Corporation
Inventor： Mahmoud Reza Ahmadi , Siavash Fallahi , Tamer Ali , Ali Nazemi , Hassan Maarefi , Burak Catli , Afshin Momtaz
CPC classification number: H04L7/0331 , H03L7/00 , H03L7/0996 , H04L7/0016
Abstract: A device for high-speed clock generation may include an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate multiple clock signals with different equally spaced phase angles. A phase-interpolator (PI) circuit may be configured to receive the multiple coarse spaced clock signals and to generate an output clock signal having a correct phase angle. The PI circuit may include a smoothing block that may be configured to smooth the multiple clock signals with different phase angles and to generate multiple smooth clock signals. A pulling block may be configured to pull edges of the multiple smooth clock signals closer to one another.
Abstract translation: 用于高速时钟产生的装置可以包括被配置为接收一个或多个输入时钟信号并且生成具有不同等间隔的相位角的多个时钟信号的注入锁定环形振荡器（ILRO）。 相位插值器（PI）电路可以被配置为接收多个粗略间隔的时钟信号并且产生具有正确相位角的输出时钟信号。 PI电路可以包括平滑块，其可以被配置为平滑具有不同相位角的多个时钟信号并且生成多个平滑时钟信号。 牵引块可以被配置成拉近多个平滑时钟信号的边缘彼此更接近。
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4.发明申请COMPACT LOW-POWER FULLY DIGITAL CMOS CLOCK GENERATION APPARATUS FOR HIGH-SPEED SERDES 有权针对高速串口的紧凑型低功耗全数字CMOS时钟发生器公开(公告)号：US20140241442A1
公开(公告)日：2014-08-28
申请号：US13946981
申请日：2013-07-19
Applicant: BROADCOM CORPORATION
Inventor： Mahmoud Reza Ahmadi , Siavash Fallahi , Tamer Ali , Ali Nazemi , Hassan Maarefi , Burak Catli , Afshin Momtaz
IPC: H03L7/00
CPC classification number: H04L7/0331 , H03L7/00 , H03L7/0996 , H04L7/0016
Abstract: A device for high-speed clock generation may include an injection locking-ring oscillator (ILRO) configured to receive one or more input clock signals and to generate multiple clock signals with different equally spaced phase angles. A phase-interpolator (PI) circuit may be configured to receive the multiple coarse spaced clock signals and to generate an output clock signal having a correct phase angle. The PI circuit may include a smoothing block that may be configured to smooth the multiple clock signals with different phase angles and to generate multiple smooth clock signals. A pulling block may be configured to pull edges of the multiple smooth clock signals closer to one another.
Abstract translation: 用于高速时钟产生的装置可以包括被配置为接收一个或多个输入时钟信号并且生成具有不同等间隔的相位角的多个时钟信号的注入锁定环形振荡器（ILRO）。 相位插值器（PI）电路可以被配置为接收多个粗略间隔的时钟信号并且产生具有正确相位角的输出时钟信号。 PI电路可以包括平滑块，其可以被配置为平滑具有不同相位角的多个时钟信号并且生成多个平滑时钟信号。 牵引块可以被配置成拉近多个平滑时钟信号的边缘彼此更接近。
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