公开(公告)号：US09197214B2

公开(公告)日：2015-11-24

申请号：US14025058

申请日：2013-09-12

Applicant: Broadcom Corporation

Inventor： Ali Nazemi ,  Kangmin Hu ,  Jun Cao ,  Afshin Doctor Momtaz

IPC: H03K19/0175 ,  H03K19/0185

CPC classification number: H03K19/018507

Abstract: A high speed level shifter interfaces a high speed DAC to the digital information that the DAC processes. The level shifter may convert CMOS level digital representations to, for example, CML level digital representations for processing by the DAC. The level shifter conserves the voltage swing in the CMOS level representations (e.g., about 1V). The level shifter also avoids voltage overstress, using a feedback loop to constrain the voltage amplitude, and thereby facilitates the use of fast thin film transistors in its architecture.

Abstract translation: 高速电平转换器将高速DAC连接到DAC处理的数字信息。 电平移位器可以将CMOS电平数字表示转换为例如CML级数字表示以供DAC进行处理。 电平移位器保存CMOS电平表示中的电压摆幅（例如，约1V）。 电平转换器还避免了电压过应力，使用反馈环来约束电压幅度，从而有助于在其架构中使用快速薄膜晶体管。

公开(公告)号：US20150084800A1

公开(公告)日：2015-03-26

申请号：US14040467

申请日：2013-09-27

Applicant: Broadcom Corporation

Inventor： Heng Zhang ,  Delong Cui ,  Jun Cao ,  Afshin Doctor Momtaz

IPC: H03M1/12

CPC classification number: H03M1/0624 ,  H03M1/00 ,  H03M1/1215

Abstract: Methods and apparatuses are described for versatile phase adjustment schemes comprising multi-layered clock skew correction with variable range and resolution to improve performance for a variety of ADC architectures, including TI-ADCs. Multi-stage phase alignment corrects misalignment in multiple stages at start-up and continuously or periodically during operation to reduce static sources of misalignment caused by design and fabrication and dynamic sources of misalignment caused by operational variations (e.g., voltage, temperature). Multi-path phase alignment corrects misalignment in the data path (e.g., analog path) and the clock path (e.g., digital path, analog path, CMOS path, CML path, or any combination thereof) for distributed alignment. Multi-lane phase alignment corrects misalignment in multiple time-interleaved signal lanes. Multi-resolution phase alignment corrects misalignment at three or more levels of resolution (e.g., coarse, fine and ultra-fine). Multi-type phase alignment corrects misalignment using different techniques (e.g., controlled current, resistance, capacitance) in a suitable path.

Abstract translation: 描述了用于通用相位调整方案的方法和装置，其包括具有可变范围和分辨率的多层时钟偏差校正，以改善包括TI-ADC在内的各种ADC架构的性能。 多级相位对准在启动时以多个阶段校正错位，并且在运行期间连续或周期性地校正不对准，以减少由设计和制造导致的静态不对准源以及由操作变化（例如，电压，温度）引起的动态不对准源。 多路径相位对准校正用于分布式对准的数据路径（例如，模拟路径）和时钟路径（例如，数字路径，模拟路径，CMOS路径，CML路径或其任何组合）中的未对准。 多通道相位对准校正多个时间交错信号通道中的未对准。 多分辨率相位校准可以在三级或更多级别的分辨率（例如，粗，细和超细）校正未对准。 多种类型的相位校正使用不同的技术（例如，受控电流，电阻，电容）在适当的路径中校正不对准。

公开(公告)号：US20150035563A1

公开(公告)日：2015-02-05

申请号：US14025058

申请日：2013-09-12

Applicant: Broadcom Corporation

Inventor： Ali Nazemi ,  Kangmin Hu ,  Jun Cao ,  Afshin Doctor Momtaz

IPC: H03K19/0185

CPC classification number: H03K19/018507

Abstract: A high speed level shifter interfaces a high speed DAC to the digital information that the DAC processes. The level shifter may convert CMOS level digital representations to, for example, CML level digital representations for processing by the DAC. The level shifter conserves the voltage swing in the CMOS level representations (e.g., about 1V). The level shifter also avoids voltage overstress, using a feedback loop to constrain the voltage amplitude, and thereby facilitates the use of fast thin film transistors in its architecture.

Abstract translation: 高速电平转换器将高速DAC连接到DAC处理的数字信息。 电平移位器可以将CMOS电平数字表示转换为例如CML级数字表示以供DAC进行处理。 电平移位器保存CMOS电平表示中的电压摆幅（例如，约1V）。 电平转换器还避免了电压过应力，使用反馈环来约束电压幅度，从而有助于在其架构中使用快速薄膜晶体管。

公开(公告)号：US20150008982A1

公开(公告)日：2015-01-08

申请号：US14042274

申请日：2013-09-30

Applicant: Broadcom Corporation

Inventor： Kuo-J Huang ,  Delong Cui ,  Jun Cao ,  Afshin Doctor Momtaz ,  Iuri Mehr ,  Ramon Alejandro Gomez

IPC: H03F1/32

CPC classification number: H03F1/3205 ,  H03F1/3211 ,  H03F1/3241 ,  Y10T29/49016

Abstract: Techniques are described herein that adaptively suppress harmonic distortion in an amplifier utilizing negative gain. The amplifier includes a first amplifier stage and a second amplifier stage, which are coupled in parallel. The first amplifier stage has a positive gain. The second amplifier stage has a negative gain to suppress total harmonic distortion of a system that includes the amplifier. The amplifier further includes shunt-peaking circuitry coupled to the first amplifier stage and the second amplifier stage to increase a maximum operating frequency at which the amplifier is capable of operating.

Abstract translation: 这里描述了利用负增益自适应地抑制放大器中的谐波失真的技术。 放大器包括并联耦合的第一放大级和第二放大级。 第一个放大器级具有正增益。 第二放大器级具有负增益以抑制包括放大器的系统的总谐波失真。 放大器还包括耦合到第一放大器级和第二放大器级的并联峰值电路，以增加放大器能够操作的最大工作频率。

公开(公告)号：US09344268B1

公开(公告)日：2016-05-17

申请号：US14668165

申请日：2015-03-25

Applicant: Broadcom Corporation

Inventor： Ali Nazemi ,  Burak Catli ,  Wayne Wah-Yuen Wong ,  Kangmin Hu ,  Hyo Gyuem Rhew ,  Delong Cui ,  Jun Cao ,  Bo Zhang ,  Afshin Doctor Momtaz

IPC: H04L7/00 ,  H04L7/033

CPC classification number: H04J3/0685 ,  H04J3/047 ,  H04L7/0025

Abstract: A phase alignment architecture enhances the performance of communication systems. The architecture aligns a divided clock (e.g., in differential Inphase (I) and Quadrature (Q)) to a main clock, even at extremely high speeds, where skew variations of the divided clock are comparable to the main clock period. The improvement in phase alignment facilitates ultra high-speed communications.

Abstract translation: 相位对准架构增强了通信系统的性能。 即使在非常高的速度下，分频时钟的分频时钟（例如，差分同相（I）和正交（Q））与主时钟对准，其中分频时钟的偏移变化与主时钟周期相当。 相位对准的改进有助于超高速通信。

公开(公告)号：US09136797B2

公开(公告)日：2015-09-15

申请号：US14042274

申请日：2013-09-30

Applicant: Broadcom Corporation

Inventor： Kuo-J Huang ,  Delong Cui ,  Jun Cao ,  Afshin Doctor Momtaz ,  Iuri Mehr ,  Ramon Alejandro Gomez

IPC: H03F3/45 ,  H03F1/32

CPC classification number: H03F1/3205 ,  H03F1/3211 ,  H03F1/3241 ,  Y10T29/49016

Abstract: Techniques are described herein that adaptively suppress harmonic distortion in an amplifier utilizing negative gain. The amplifier includes a first amplifier stage and a second amplifier stage, which are coupled in parallel. The first amplifier stage has a positive gain. The second amplifier stage has a negative gain to suppress total harmonic distortion of a system that includes the amplifier. The amplifier further includes shunt-peaking circuitry coupled to the first amplifier stage and the second amplifier stage to increase a maximum operating frequency at which the amplifier is capable of operating.

Abstract translation: 这里描述了利用负增益自适应地抑制放大器中的谐波失真的技术。 放大器包括并联耦合的第一放大级和第二放大级。 第一个放大器级具有正增益。 第二放大器级具有负增益以抑制包括放大器的系统的总谐波失真。 放大器还包括耦合到第一放大器级和第二放大器级的并联峰值电路，以增加放大器能够操作的最大工作频率。

公开(公告)号：US09065464B2

公开(公告)日：2015-06-23

申请号：US14040467

申请日：2013-09-27

Applicant: Broadcom Corporation

Inventor： Heng Zhang ,  Delong Cui ,  Jun Cao ,  Afshin Doctor Momtaz

IPC: H03M1/12 ,  H03M1/00

CPC classification number: H03M1/0624 ,  H03M1/00 ,  H03M1/1215

Abstract: Methods and apparatuses are described for versatile phase adjustment schemes comprising multi-layered clock skew correction with variable range and resolution to improve performance for a variety of ADC architectures, including TI-ADCs. Multi-stage phase alignment corrects misalignment in multiple stages at start-up and continuously or periodically during operation to reduce static sources of misalignment caused by design and fabrication and dynamic sources of misalignment caused by operational variations (e.g., voltage, temperature). Multi-path phase alignment corrects misalignment in the data path (e.g., analog path) and the clock path (e.g., digital path, analog path, CMOS path, CML path, or any combination thereof) for distributed alignment. Multi-lane phase alignment corrects misalignment in multiple time-interleaved signal lanes. Multi-resolution phase alignment corrects misalignment at three or more levels of resolution (e.g., coarse, fine and ultra-fine). Multi-type phase alignment corrects misalignment using different techniques (e.g., controlled current, resistance, capacitance) in a suitable path.

Abstract translation: 描述了用于通用相位调整方案的方法和装置，其包括具有可变范围和分辨率的多层时钟偏差校正，以改善包括TI-ADC在内的各种ADC架构的性能。 多级相位对准在启动时以多个阶段校正错位，并且在运行期间连续或周期性地校正不对准，以减少由设计和制造导致的静态不对准源以及由操作变化（例如，电压，温度）引起的动态不对准源。 多路径相位对准校正用于分布式对准的数据路径（例如，模拟路径）和时钟路径（例如，数字路径，模拟路径，CMOS路径，CML路径或其任何组合）中的未对准。 多通道相位对准校正多个时间交错信号通道中的未对准。 多分辨率相位校准可以在三级或更多级别的分辨率（例如，粗，细和超细）校正未对准。 多种类型的相位校正使用不同的技术（例如，受控电流，电阻，电容）在适当的路径中校正不对准。