公开(公告)号：US09065464B2

公开(公告)日：2015-06-23

申请号：US14040467

申请日：2013-09-27

Applicant: Broadcom Corporation

Inventor： Heng Zhang ,  Delong Cui ,  Jun Cao ,  Afshin Doctor Momtaz

IPC: H03M1/12 ,  H03M1/00

CPC classification number: H03M1/0624 ,  H03M1/00 ,  H03M1/1215

Abstract: Methods and apparatuses are described for versatile phase adjustment schemes comprising multi-layered clock skew correction with variable range and resolution to improve performance for a variety of ADC architectures, including TI-ADCs. Multi-stage phase alignment corrects misalignment in multiple stages at start-up and continuously or periodically during operation to reduce static sources of misalignment caused by design and fabrication and dynamic sources of misalignment caused by operational variations (e.g., voltage, temperature). Multi-path phase alignment corrects misalignment in the data path (e.g., analog path) and the clock path (e.g., digital path, analog path, CMOS path, CML path, or any combination thereof) for distributed alignment. Multi-lane phase alignment corrects misalignment in multiple time-interleaved signal lanes. Multi-resolution phase alignment corrects misalignment at three or more levels of resolution (e.g., coarse, fine and ultra-fine). Multi-type phase alignment corrects misalignment using different techniques (e.g., controlled current, resistance, capacitance) in a suitable path.

Abstract translation: 描述了用于通用相位调整方案的方法和装置，其包括具有可变范围和分辨率的多层时钟偏差校正，以改善包括TI-ADC在内的各种ADC架构的性能。 多级相位对准在启动时以多个阶段校正错位，并且在运行期间连续或周期性地校正不对准，以减少由设计和制造导致的静态不对准源以及由操作变化（例如，电压，温度）引起的动态不对准源。 多路径相位对准校正用于分布式对准的数据路径（例如，模拟路径）和时钟路径（例如，数字路径，模拟路径，CMOS路径，CML路径或其任何组合）中的未对准。 多通道相位对准校正多个时间交错信号通道中的未对准。 多分辨率相位校准可以在三级或更多级别的分辨率（例如，粗，细和超细）校正未对准。 多种类型的相位校正使用不同的技术（例如，受控电流，电阻，电容）在适当的路径中校正不对准。

公开(公告)号：US20140126613A1

公开(公告)日：2014-05-08

申请号：US13671340

申请日：2012-11-07

Applicant: BROADCOM CORPORATION

Inventor： Heng Zhang ,  Mehdi Khanpour ,  Jun Cao ,  Chang Liu ,  Afshin Momtaz

IPC: H03D3/02

CPC classification number: H04B1/745 ,  H03D3/006 ,  H03D3/02 ,  H04L7/033

Abstract: Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.

Abstract translation: 描述了减少收发器中的延迟的方法，系统和装置。 收发器包括高延迟通信信道和被配置为高延迟通信信道的旁路信道的低延迟通信信道。 当在低延迟应用中使用收发器时，可以利用低延迟通信信道。 通过绕过高延迟通信信道，可以避免其中引入的高等待时间（由于用于减少数字处理的数据速率的许多解除序列化阶段）。 当低延迟通信信道用于传递数据时，实现数据速率的增加。 可以使用延迟锁定环（DLL）将收发器的发射机时钟与收发器的接收机时钟相位对准，以补偿这些时钟之间的相位偏移的有限公差。

公开(公告)号：US08873606B2

公开(公告)日：2014-10-28

申请号：US13671340

申请日：2012-11-07

Applicant: Broadcom Corporation

Inventor： Heng Zhang ,  Mehdi Khanpour ,  Jun Cao ,  Chang Liu ,  Afshin Momtaz

IPC: H04B1/38 ,  H03D3/02

CPC classification number: H04B1/745 ,  H03D3/006 ,  H03D3/02 ,  H04L7/033

Abstract: Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.

Abstract translation: 描述了减少收发器中的延迟的方法，系统和装置。 收发器包括高延迟通信信道和被配置为高延迟通信信道的旁路信道的低延迟通信信道。 当在低延迟应用中使用收发器时，可以利用低延迟通信信道。 通过绕过高延迟通信信道，可以避免其中引入的高等待时间（由于用于减少数字处理的数据速率的许多解除序列化阶段）。 当低延迟通信信道用于传递数据时，实现数据速率的增加。 可以使用延迟锁定环（DLL）将收发器的发射机时钟与收发器的接收机时钟相位对准，以补偿这些时钟之间的相位偏移的有限公差。

公开(公告)号：US08836553B2

公开(公告)日：2014-09-16

申请号：US13754374

申请日：2013-01-30

Applicant: Broadcom Corporation

Inventor： Bo Zhang ,  Ali Nazemi ,  Mahmoud Reza Ahmadi ,  Afshin Momtaz ,  Heng Zhang ,  Hassan Maarefi

IPC: H03M1/10

CPC classification number: H03M1/1009 ,  H03M1/069 ,  H03M1/1023 ,  H03M1/141 ,  H03M1/188 ,  H03M1/361

Abstract: Methods and apparatuses are described for a DSP receiver with an analog-to-digital converter (ADC) having high speed, low BER performance with low power and area requirements. Speed is increased for multi-path ADC configurations by resolving a conventional bottleneck. ADC performance is improved by integrating calibration and error detection and correction, such as distributed offset calibration and redundant comparators. Power and area requirements are dramatically reduced by using low BER rectification to nearly halve the number of comparators in a conventional high speed, low BER flash ADC.

Abstract translation: 描述了具有模数转换器（ADC）的DSP接收机的方法和装置，具有高速度，低BER性能，低功率和面积要求。 通过解决传统的瓶颈，提高了多路径ADC配置的速度。 通过集成校准和错误检测和校正（例如分布式偏移校准和冗余比较器）来提高ADC性能。 通过使用低BER整流将传统高速，低BER闪存ADC中的比较器数量减半，功率和面积要求大大降低。

公开(公告)号：US20150084800A1

公开(公告)日：2015-03-26

申请号：US14040467

申请日：2013-09-27

Applicant: Broadcom Corporation

Inventor： Heng Zhang ,  Delong Cui ,  Jun Cao ,  Afshin Doctor Momtaz

IPC: H03M1/12

CPC classification number: H03M1/0624 ,  H03M1/00 ,  H03M1/1215

Abstract: Methods and apparatuses are described for versatile phase adjustment schemes comprising multi-layered clock skew correction with variable range and resolution to improve performance for a variety of ADC architectures, including TI-ADCs. Multi-stage phase alignment corrects misalignment in multiple stages at start-up and continuously or periodically during operation to reduce static sources of misalignment caused by design and fabrication and dynamic sources of misalignment caused by operational variations (e.g., voltage, temperature). Multi-path phase alignment corrects misalignment in the data path (e.g., analog path) and the clock path (e.g., digital path, analog path, CMOS path, CML path, or any combination thereof) for distributed alignment. Multi-lane phase alignment corrects misalignment in multiple time-interleaved signal lanes. Multi-resolution phase alignment corrects misalignment at three or more levels of resolution (e.g., coarse, fine and ultra-fine). Multi-type phase alignment corrects misalignment using different techniques (e.g., controlled current, resistance, capacitance) in a suitable path.

Abstract translation: 描述了用于通用相位调整方案的方法和装置，其包括具有可变范围和分辨率的多层时钟偏差校正，以改善包括TI-ADC在内的各种ADC架构的性能。 多级相位对准在启动时以多个阶段校正错位，并且在运行期间连续或周期性地校正不对准，以减少由设计和制造导致的静态不对准源以及由操作变化（例如，电压，温度）引起的动态不对准源。 多路径相位对准校正用于分布式对准的数据路径（例如，模拟路径）和时钟路径（例如，数字路径，模拟路径，CMOS路径，CML路径或其任何组合）中的未对准。 多通道相位对准校正多个时间交错信号通道中的未对准。 多分辨率相位校准可以在三级或更多级别的分辨率（例如，粗，细和超细）校正未对准。 多种类型的相位校正使用不同的技术（例如，受控电流，电阻，电容）在适当的路径中校正不对准。

公开(公告)号：US20150010044A1

公开(公告)日：2015-01-08

申请号：US14498383

申请日：2014-09-26

Applicant: Broadcom Corporation

Inventor： Heng Zhang ,  Mehdi Khanpour ,  Jun Cao ,  Chang Liu ,  Afshin Momtaz

IPC: H04B1/74 ,  H04L7/033

CPC classification number: H04B1/745 ,  H03D3/006 ,  H03D3/02 ,  H04L7/033

Abstract: Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.

Abstract translation: 描述了减少收发器中的延迟的方法，系统和装置。 收发器包括高延迟通信信道和被配置为高延迟通信信道的旁路信道的低延迟通信信道。 当在低延迟应用中使用收发器时，可以利用低延迟通信信道。 通过绕过高延迟通信信道，可以避免其中引入的高等待时间（由于用于减少数字处理的数据速率的许多解除序列化阶段）。 当低延迟通信信道用于传递数据时，实现数据速率的增加。 可以使用延迟锁定环（DLL）将收发器的发射机时钟与收发器的接收机时钟相位对准，以补偿这些时钟之间的相位偏移的有限公差。

公开(公告)号：US09306621B2

公开(公告)日：2016-04-05

申请号：US14498383

申请日：2014-09-26

Applicant: Broadcom Corporation

Inventor： Heng Zhang ,  Mehdi Khanpour ,  Jun Cao ,  Chang Liu ,  Afshin Momtaz

IPC: H04B1/74 ,  H03D3/02 ,  H03D3/00 ,  H04L7/033

CPC classification number: H04B1/745 ,  H03D3/006 ,  H03D3/02 ,  H04L7/033

Abstract: Methods, systems, and apparatuses are described for reducing the latency in a transceiver. A transceiver includes a high latency communication channel and a low latency communication channel that is configured to be a bypass channel for the high latency communication channel. The low latency communication channel may be utilized when implementing the transceiver is used in low latency applications. By bypassing the high latency communication channel, the high latency that is introduced therein (due to the many stages of de-serialization used to reduce the data rate for digital processing) can be avoided. An increase in data rate is realized when the low latency communication channel is used to pass data. A delay-locked loop (DLL) may be used to phase align the transmitter clock of the transceiver with the receiver clock of the transceiver to compensate for a limited tolerance of phase offset between these clocks.

Abstract translation: 描述了减少收发器中的延迟的方法，系统和装置。 收发器包括高延迟通信信道和被配置为高延迟通信信道的旁路信道的低延迟通信信道。 当在低延迟应用中使用收发器时，可以利用低延迟通信信道。 通过绕过高延迟通信信道，可以避免其中引入的高等待时间（由于用于减少数字处理的数据速率的许多解除序列化阶段）。 当低延迟通信信道用于传递数据时，实现数据速率的增加。 可以使用延迟锁定环（DLL）将收发器的发射机时钟与收发器的接收机时钟相位对准，以补偿这些时钟之间的相位偏移的有限公差。

公开(公告)号：US08902094B1

公开(公告)日：2014-12-02

申请号：US14087457

申请日：2013-11-22

Applicant: Broadcom Corporation

Inventor： Heng Zhang ,  Delong Cui ,  Jun Cao

IPC: H03M1/00 ,  H03M1/08 ,  H03M1/50 ,  H03M1/12 ,  H03L7/081 ,  H04L7/00 ,  H03K5/135 ,  H03L7/089

CPC classification number: H03M1/08 ,  H03K5/135 ,  H03L7/0812 ,  H03L7/0814 ,  H03L7/0891 ,  H03M1/00 ,  H03M1/12 ,  H03M1/1215 ,  H04L7/0008

Abstract: A first clock generator receives an input clock, generates a first clock signal for use in a first level of a multilevel track and hold circuit of a time-interleaved analog to digital convertor, and generates a time-leading version of the first clock signal. A plurality of second clock generators receive the input clock and generate a corresponding plurality of second clock signals for use in a second level of the multi-level track and hold circuit. The plurality of second level clock generators include an adjustable delay that delays a corresponding one of the plurality of second clock signals by a delay amount that is determined based on a delay control signal. A feedback controller generates the delay control signal based on the time-leading version of the first clock signal and further based on the corresponding one of the plurality of second clock signals.

Abstract translation: 第一时钟发生器接收输入时钟，产生用于时间交织的模数转换器的多电平跟踪和保持电路的第一电平的第一时钟信号，并产生第一时钟信号的时间领先的版本。 多个第二时钟发生器接收输入时钟并产生对应的多个第二时钟信号，以在多电平跟踪和保持电路的第二电平中使用。 多个第二电平时钟发生器包括可调节的延迟，其延迟多个第二时钟信号中的相应一个第二时钟信号的延迟量，该延迟量基于延迟控制信号确定。 反馈控制器基于第一时钟信号的时间引导版本并且还基于多个第二时钟信号中的相应一个产生延迟控制信号。

公开(公告)号：US20140104086A1

公开(公告)日：2014-04-17

申请号：US13754374

申请日：2013-01-30

Applicant: BROADCOM CORPORATION

Inventor： Bo Zhang ,  Ali Nazemi ,  Mahmoud Reza Ahmadi ,  Afshin Momtaz ,  Heng Zhang ,  Hassan Maarefi

IPC: H03M1/10 ,  H03M1/36

CPC classification number: H03M1/1009 ,  H03M1/069 ,  H03M1/1023 ,  H03M1/141 ,  H03M1/188 ,  H03M1/361

Abstract: Methods and apparatuses are described for a DSP receiver with an analog-to-digital converter (ADC) having high speed, low BER performance with low power and area requirements. Speed is increased for multi-path ADC configurations by resolving a conventional bottleneck. ADC performance is improved by integrating calibration and error detection and correction, such as distributed offset calibration and redundant comparators. Power and area requirements are dramatically reduced by using low BER rectification to nearly halve the number of comparators in a conventional high speed, low BER flash ADC.

Abstract translation: 描述了具有模数转换器（ADC）的DSP接收机的方法和装置，具有高速度，低BER性能，低功率和面积要求。 通过解决传统的瓶颈，提高了多路径ADC配置的速度。 通过集成校准和错误检测和校正（例如分布式偏移校准和冗余比较器）来提高ADC性能。 通过使用低BER整流将传统高速，低BER闪存ADC中的比较器数量减半，功率和面积要求大大降低。