公开(公告)号：US20130243072A1

公开(公告)日：2013-09-19

申请号：US13871831

申请日：2013-04-26

Applicant: BROADCOM CORPORATION

Inventor： Vivek Telang ,  Hong Chen ,  Vasudevan Parthasarathy ,  Jun Cao ,  Afshin Momtaz ,  Ali Ghiasi ,  Chung-Jue Chen

IPC: H04L27/00

CPC classification number: H04L27/0002 ,  H04B1/0007 ,  H04B1/406

Abstract: According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.

Abstract translation: 根据示例性实施例，通信接收机可以包括被配置为放大接收信号的可变增益放大器（VGA），被配置为控制VGA的VGA控制器，耦合到所述接收信号的输出的多个模数转换器 VGA，其中当所述通信接收器被配置为处理第一通信协议的信号时，所述多个ADC电路是可操作的，并且其中当所述通信接收器被配置为处理第二通信协议的信号时，只有所述ADC电路的子集可操作 。

公开(公告)号：US09077328B1

公开(公告)日：2015-07-07

申请号：US14246836

申请日：2014-04-07

Applicant: Broadcom Corporation

Inventor： Magesh Valliappan ,  Afshin Momtaz ,  Namik Kocaman ,  Vasudevan Parthasarathy

IPC: H04L27/06 ,  H03K5/26 ,  H04L7/033 ,  H04B7/155

CPC classification number: H03K5/26 ,  H04B7/155 ,  H04L7/033

Abstract: Reference-less repeating circuits provide significant advantages over repeating circuits requiring external frequency references. These repeating circuits eliminate the need for external frequency references provide significant power, layout, and physical isolation advantages. Digitally controlled reference-less repeating circuits have a relatively narrow frequency detection range, but typically consume significantly less power than analog repeating circuits while providing data rate flexibility, particularly at lower data rates. Due to the narrow frequency detection range of digitally controlled reference-less repeating circuits, efficient frequency estimation techniques allow these circuits to quickly lock to an input signal, and provide an accurate repeated output signal.

Abstract translation: 无需外部频率参考的无需重复电路可提供超过重复电路的显着优点。 这些重复电路消除了对外部频率参考的需求，提供了显着的功率，布局和物理隔离优势。 数字控制的无参考中继电路具有相对较窄的频率检测范围，但是通常比模拟重复电路消耗明显更少的功率，同时提供数据速率灵活性，特别是在较低的数据速率下。 由于数字控制的无参考中继电路的窄频率检测范围，有效的频率估计技术允许这些电路快速锁定到输入信号，并提供准确的重复输出信号。

公开(公告)号：US09031178B2

公开(公告)日：2015-05-12

申请号：US14041924

申请日：2013-09-30

Applicant: Broadcom Corporation

Inventor： William Bliss ,  Vasudevan Parthasarathy

IPC: H03K7/02 ,  H04L25/03 ,  H04L27/04 ,  H04B10/25

CPC classification number: H04B10/25 ,  H04B2210/254 ,  H04L25/03343 ,  H04L25/4975

Abstract: Systems that allow for DFE functionality to be eliminated from the receiver side of a communication system and for a DFE-like functionality to be implemented instead at the transmitter side of the communication system are provided. By removing the DFE functionality from the receiver side, error propagation can be eliminated at the receiver and receiver complexity can be reduced drastically. At the transmitter side, the DFE-like functionality provides the same DFE benefits, and with the transmitter environment being noise-free, no errors can occur due noise boosting, for example. The DFE-like functionality at the transmitter side can be implemented using non-linear (recursive or feed-forward) pre-coders or a combination of non-linear pre-coders and linear filters, which can be configured to invert a net communication channel between the transmitter and the receiver. Embodiments particularly suitable for fiber optic channels and server backplane channels are also provided.

Abstract translation: 提供了允许从通信系统的接收机侧消除DFE功能并且在通信系统的发射机侧实现类似DFE的功能的系统。 通过从接收机侧去除DFE功能，可以在接收机处消除误差传播，并且可以显着降低接收机的复杂度。 在发射机侧，类似DFE的功能提供了相同的DFE优点，并且在发射机环境无噪声的情况下，例如，噪声提升不会发生错误。 可以使用非线性（递归或前馈）预编码器或非线性预编码器和线性滤波器的组合来实现发射机侧的类似DFE的功能，其可被配置为反转净通信信道 在发射机和接收机之间。 还提供了特别适用于光纤通道和服务器背板通道的实施例。

公开(公告)号：US20160182156A1

公开(公告)日：2016-06-23

申请号：US14611181

申请日：2015-01-31

Applicant: Broadcom Corporation

Inventor： Frederick Sugihwo Tang ,  Vasudevan Parthasarathy ,  John Szeming Wang ,  Rajiv Pancholy

IPC: H04B10/61

CPC classification number: H04B10/616 ,  H04B10/69

Abstract: A system includes an adjustable receiver a data line, a communications bus, and signal processing circuitry. The adjustable receiver may receive a signal and pass the received signal to the signal processing circuitry for data recovery and processing. For example, the adjustable receiver may detect an optical signal and pass the detected signal to signal processing circuitry for analog-to-digital conversion and digital processing. The signal processing circuitry may apply criteria to received signal to determine adjustment of selected parameters for the adjustable receiver. The signal processing circuitry may access addressable parameters in the adjustable receiver via the communications bus. By addressing the parameters the signal processing circuitry may apply the determined adjustments to the selected parameters in the adjustable receiver.

Abstract translation: 系统包括可调接收器，数据线，通信总线和信号处理电路。 可调接收器可以接收信号并将接收到的信号传递到信号处理电路以用于数据恢复和处理。 例如，可调节接收器可以检测光信号并将检测到的信号传递到用于模数转换和数字处理的信号处理电路。 信号处理电路可以将接收信号的标准应用于可调接收机的选定参数的调整。 信号处理电路可经由通信总线访问可调节接收机中的可寻址参数。 通过寻址参数，信号处理电路可以将所确定的调整应用于可调节接收机中的所选择的参数。

公开(公告)号：US08964907B2

公开(公告)日：2015-02-24

申请号：US13871831

申请日：2013-04-26

Applicant: Broadcom Corporation

Inventor： Vivek Pundlik Telang ,  Hong Chen ,  Vasudevan Parthasarathy ,  Jun Cao ,  Afshin Momtaz ,  Ali Ghiasi ,  Chung-Jue Chen

IPC: H03D1/00 ,  H04L27/06 ,  H04L27/00 ,  H04B1/00

CPC classification number: H04L27/0002 ,  H04B1/0007 ,  H04B1/406

Abstract: According to an example embodiment, a communications receiver may include a variable gain amplifier (VGA) configured to amplify received signals, a VGA controller configured to control the VGA, a plurality of analog to digital converter (ADC) circuits coupled to an output of the VGA, wherein the plurality of ADC circuits are operational when the communications receiver is configured to process signals of a first communications protocol, and wherein only a subset of the ADC circuits are operational when the communications receiver is configured to process signals of a second communications protocol.

Abstract translation: 根据示例性实施例，通信接收机可以包括被配置为放大接收信号的可变增益放大器（VGA），被配置为控制VGA的VGA控制器，耦合到所述接收信号的输出的多个模数转换器 VGA，其中当所述通信接收器被配置为处理第一通信协议的信号时，所述多个ADC电路是可操作的，并且其中当所述通信接收器被配置为处理第二通信协议的信号时，只有所述ADC电路的子集可操作 。

公开(公告)号：US09270291B1

公开(公告)日：2016-02-23

申请号：US14662001

申请日：2015-03-18

Applicant: Broadcom Corporation

Inventor： Gavin D. Parnaby ,  Vasudevan Parthasarathy ,  John S. Wang

IPC: H03M1/12 ,  H03M1/10 ,  H04B17/21 ,  H04L7/00

CPC classification number: H03M1/121 ,  H03M1/0836 ,  H03M1/1028 ,  H03M1/1215 ,  H03M1/1245 ,  H04B17/21 ,  H04L7/0004

Abstract: Methods and apparatuses are described for timing skew mitigation in time-interleaved ADCs (TI-ADCs) that may be performed for any receive signal without any special signals during blind initialization, which may be followed by background calibration. The same gain/skew calibration metrics may be applied to baud sampled and oversampled systems, including wideband receivers and regardless of any modulation, by applying a timing or frequency offset to non-stationary sampled signals during initial training. Skew mitigation is low latency, low power, low area, noise tolerant and scalable. Digital estimation may be implemented with accumulators and multipliers while analog calibration may be implemented with adjustable delays. DC and gain offsets may be calibrated before skew calibration. The slope of the correlation function between adjacent samples may be used to move a timing skew estimate stochastically at a low adaptive rate until the skew algorithm converges.

Abstract translation: 描述了用于在盲初始化期间可以对任何接收信号执行任何特殊信号的时间交织ADC（TI-ADC）中的定时偏移缓解的方法和装置，其可以在背景校准之后进行。 相同的增益/偏斜校准度量可以应用于波特率采样和过采样系统，包括宽带接收机，无论任何调制，通过在初始训练期间对非平稳采样信号应用定时或频率偏移。 倾斜减轻是低延迟，低功率，低面积，噪声容限和可扩展性。 数字估计可以用累加器和乘法器来实现，而模拟校准可以用可调延迟来实现。 在校准偏差之前可以校准直流和增益偏移。 相邻样本之间的相关函数的斜率可以用于以低自适应速率随机移动定时偏差估计，直到偏斜算法收敛。

公开(公告)号：US09041571B2

公开(公告)日：2015-05-26

申请号：US14020529

申请日：2013-09-06

Applicant: Broadcom Corporation

Inventor： John Wang ,  Vasudevan Parthasarathy

IPC: H03M1/10 ,  H03M1/12

CPC classification number: H03M1/1205 ,  H03M1/1038 ,  H03M1/12 ,  H03M1/121

Abstract: Systems and methods are provided for calibrating an analog to digital converter (ADC) using one or more feedback mechanisms. In an embodiment, a capture memory module captures a portion of ADC data and post-processes the captured data using a microprocessor to perform calibration. Using the microprocessor, the capture memory module calibrates the ADC until the output of the ADC is within a desired range. In an embodiment, the capture memory module also captures a portion of data output from a digital correction module and post-processes this captured data using the microprocessor. Using the microprocessor, the capture memory module calibrates the digital correction module until the output of the digital correction module is within a desired range.

Abstract translation: 提供了使用一个或多个反馈机制来校准模数转换器（ADC）的系统和方法。 在一个实施例中，捕获存储器模块捕获一部分ADC数据，并使用微处理器对所捕获的数据进行后处理以执行校准。 使用微处理器，捕获存储器模块校准ADC，直到ADC的输出在所需的范围内。 在一个实施例中，捕获存储器模块还捕获从数字校正模块输出的一部分数据，并且使用微处理器对该捕获的数据进行后处理。 使用微处理器，捕获存储器模块校准数字校正模块，直到数字校正模块的输出在期望的范围内。

公开(公告)号：US08990654B2

公开(公告)日：2015-03-24

申请号：US14136120

申请日：2013-12-20

Applicant: Broadcom Corporation

Inventor： William Bliss ,  Vasudevan Parthasarathy

IPC: H03M13/00 ,  H03M13/15 ,  H03M13/05 ,  H04L1/00 ,  H04L25/49 ,  H04B7/04 ,  H04L25/03 ,  H04L27/02 ,  H04L27/00

CPC classification number: H03M13/151 ,  H03M13/05 ,  H03M13/1515 ,  H04B7/0456 ,  H04L1/0041 ,  H04L1/0045 ,  H04L1/0057 ,  H04L25/03949 ,  H04L25/4917 ,  H04L27/00 ,  H04L27/02

Abstract: In conventional Backplane Ethernet systems, data is transmitted over two pairs of copper traces in one direction using a PAM-2 scheme and a baud rate of 10.3125 GHz, giving an effective bit rate of 10.3125 Gbps. The rate at which data can be transmitted in Backplane Ethernet systems, while still being reliably received, is typically limited by ISI caused by the dispersive nature of the copper traces, frequency dependent transmission losses caused primarily by skin effect and dielectric loss of the copper traces, and cross-talk from adjacent communication lines. The present invention is directed to systems for overcoming these and other signal impairments to achieve speeds up to, and beyond, twice the conventional 10 Gbps limit associated with Backplane Ethernet systems.

Abstract translation: 在传统的背板以太网系统中，使用PAM-2方案和10.3125 GHz的波特率，通过两对铜线路在一个方向上传输数据，给出10.3125 Gbps的有效比特率。 在背板以太网系统中数据传输的速率仍然可靠地接收，通常受到铜迹线色散性质引起的ISI的限制，主要由皮肤效应引起的频率依赖传输损耗和铜迹线的介电损耗 ，以及相邻通信线路的串扰。 本发明涉及用于克服这些和其他信号损伤的系统，以实现高达和超过与背板以太网系统相关联的常规10Gbps限制的两倍的速度。