公开(公告)号：US3790412A

公开(公告)日：1974-02-05

申请号：US3790412D

申请日：1972-04-07

Applicant: BELL TELEPHONE LABOR INC

Inventor： MOLINE R

IPC: F01D5/30 ,  H01L21/00 ,  H01L21/265 ,  H01L21/266 ,  H01L7/54

CPC classification number: H01L21/265 ,  F01D5/30 ,  H01L21/00 ,  H01L21/266 ,  Y10S148/106 ,  Y10S438/944

Abstract: Thermal expansion of shadow masks used in ion implantation processes has been found to cause inaccuracies in the ion implanted pattern. Such inaccuracies are reduced or eliminated by first directing a heating current into the mask, monitoring the resistance of the mask, and controlling the heating current in accordance with monitored resistance. As the mask is bombarded with ions, any temperature rise increases the monitored resistance to automatically reduce the heating current, thus compensating for the thermal effect of ion bombardment.

Abstract translation: 已经发现离子注入工艺中使用的荫罩的热膨胀导致离子注入图案中的不准确。 通过首先将加热电流引导到掩模中，监测掩模的电阻，并根据被监视的电阻来控制加热电流来减少或消除这种不准确。 当掩模用离子轰击时，任何温度升高都会增加监控电阻，自动降低加热电流，从而补偿离子轰击的热效应。

公开(公告)号：US3767492A

公开(公告)日：1973-10-23

申请号：US3767492D

申请日：1971-10-12

Applicant: BELL TELEPHONE LABOR INC

Inventor： MAC RAE A ,  MOLINE R

IPC: H01L21/033 ,  H01L23/29 ,  H01L7/00

CPC classification number: H01L23/29 ,  H01L21/0332 ,  H01L21/0337 ,  H01L23/291 ,  H01L2924/0002 ,  Y10S148/043 ,  Y10S148/051 ,  Y10S148/114 ,  H01L2924/00

Abstract: The specification describes a masking technique for semiconductor processing in which the usual photolithographic mask is eliminated by the use of an ion beam resist technique. The ion beam exposure is performed through a shadow mask. The mask layer comprises a dual dielectric. Preferential etching of the exposed portions of the top layer is used initially to form the pattern and the patterned top layer is used as a mask for the underlayer. This is advantageous when the preferential etch ratio between the composite materials substantially exceeds the available etch ratio between the beam-exposed material and the unexposed material. The use of SiO2-Si3N4 and SiO2-Al2O3 composites are suggested. Ion-bombarded Si3N4 has been found to be susceptible to etching in HF so that a single etchant can be used for both layers of the SiO2-Si3N4 composite.

Abstract translation: 该说明书描述了半导体处理的掩模技术，其中通过使用离子束抗蚀剂技术消除了通常的光刻掩模。 通过荫罩进行离子束曝光。 掩模层包括双电介质。 首先使用顶层的暴露部分的优先蚀刻来形成图案，并且将图案化的顶层用作底层的掩模。 当复合材料之间的优选蚀刻比基本上超过曝光材料和未曝光材料之间的可用蚀刻比时，这是有利的。

公开(公告)号：US3728161A

公开(公告)日：1973-04-17

申请号：US3728161D

申请日：1971-12-28

Applicant: BELL TELEPHONE LABOR INC

Inventor： MOLINE R

IPC: H01L29/78 ,  H01L21/265 ,  H01L21/76 ,  H01L21/768 ,  H01L23/522 ,  H01L27/088 ,  H01L29/06 ,  H01L29/41 ,  H01L7/54

CPC classification number: H01L29/0638 ,  H01L21/26513 ,  H01L21/2652 ,  H01L27/088 ,  Y10S438/919

Abstract: D R A W I N G
THE SPECIFICATION DESCRIBES A CHAN STOP TECHNIQUE FOR ELIMINATING SPURIOUS INVERSION OF THE SURFACE OF A SEMICONDUCTOR INTEGRATED CIRCUIT CHIP DUE TO CAPACITIVE COUPLING BBETWEEN THE METALLIZATION AND/OR THE FIELD OXIDE AND THE SEMICONDUCTOR. SPURIOUS INVERSION IS CONVENTIONALLY OVERCOME BY PROVIDING A LOW RESISTIVITY REGION, COMMONLY REFERRED TO AS A CHAN STOP, UNIFORRMLY UNDER THE FIELD OXIDE. IN MAKING DEVICES USING ION IMPLATION TECHNIQUES, THE CHANNEL OR ACTIVE REGION IS FIRST MASKED AND THE CHAN STOP IS FORMED BY IMPLANTATION OR DIFFUSION. AFTER THE FIELD OXIDE IS GROWN, THE MASK FOR FORMING THE CHANNEL WINDOW MUST BE ALIGNED WITH THE REGION PREVIOUSLY MASKED. THIS ALIGNMENT AND THE FIRST MASKING STEP ARE ELIMINATED IN THE PROCESS DESCRIBED BY FORMING A UNIFORM CHAN STOP IMPLANT AND COMPENSATING THE CHAN STOP IMPURITIES IN THE CHANNEL REGION BY A COMPENSATION IMPLANT THROUGH THE CHANNEL WINDOW. THE CHAN STOP AND CHANNEL ARE THEREBY SELF-ALIGNED.

公开(公告)号：US3792452A

公开(公告)日：1974-02-12

申请号：US3792452D

申请日：1971-06-10

Applicant: BELL TELEPHONE LABOR INC

Inventor： NORTH J ,  VARNERIN L ,  DIXON M ,  MOLINE R ,  WOLFE R

IPC: C04B35/26 ,  G11C19/08 ,  H01F10/20 ,  H01F10/24 ,  H01F41/18

CPC classification number: H01F10/20 ,  C04B35/26 ,  G11C19/08 ,  H01F10/24 ,  H01F41/186

Abstract: Magnetic anisotropy in oxidic magnetic materials is altered by strain which is induced by local expansion of the lattice through ion implantation. This compressional strain in the instance of a material having positive magnetostriction may result in an enhanced magnetic easy direction normal to a major surface. Exemplary rare earth iron garnet materials have been so processed as to result in a thin surface region having appropriate magnetic properties for incorporation in ''''bubble'''' devices.

Abstract translation: 氧化磁性材料中的磁各向异性由通过离子注入的晶格的局部膨胀引起的应变改变。 在具有正磁致伸缩的材料的情况下的这种压缩应变可导致与主表面垂直的增强的磁性容易方向。 已经对典型的稀土铁石榴石材料进行了处理，以形成具有合适磁性的薄表面区域，以便结合到“气泡”装置中。

公开(公告)号：US3717790A

公开(公告)日：1973-02-20

申请号：US3717790D

申请日：1971-06-24

Applicant: BELL TELEPHONE LABOR INC

Inventor： MATHEWS J ,  MOLINE R ,  DALTON J ,  MACRAE A ,  PICKAR K ,  SEIDEL H

IPC: H01J9/233 ,  H01L21/00 ,  H01L27/00 ,  H01L17/00 ,  H01L15/00

CPC classification number: H01L21/00 ,  H01J9/233 ,  H01L27/00

Abstract: The specification describes processes using ion implantation for preparing silicon diode array targets for video camera tubes. Bulk silicon prepared in the conventional way has sufficient nonuniformity over the target area to produce contrast patterns in the video output. This effect can be eliminated by initially preparing high resistivity bulk material and implanting the bulk impurities to obtain the desired bulk resistivity. Advantageous procedures for implanting the diodes are also described.

Abstract translation: 该说明书描述了使用离子注入来制备用于摄像机管的硅二极管阵列靶的工艺。 以常规方式制备的散装硅在目标区域上具有足够的不均匀性，以在视频输出中产生对比度图案。 通过初始制备高电阻率散装材料并植入大块杂质以获得所需的体电阻率，可以消除这种影响。 还描述了用于注入二极管的有利程序。

公开(公告)号：US3769109A

公开(公告)日：1973-10-30

申请号：US3769109D

申请日：1972-04-19

Applicant: BELL TELEPHONE LABOR INC

Inventor： MAC RAE A ,  MOLINE R

IPC: H01L23/29 ,  H01L7/50

CPC classification number: H01L21/31155 ,  H01L21/266 ,  H01L23/291 ,  H01L2924/0002 ,  Y10S148/02 ,  Y10S148/041 ,  Y10S148/042 ,  Y10S148/053 ,  Y10S148/106 ,  Y10S438/924 ,  Y10S438/978 ,  H01L2924/00

Abstract: During SiO2 etching, when the oxide surface etch rate is larger than the bulk etch rate and the photoresist adheres tenaciously to the surface, a near vertical wall or cusp will be formed. This will create potential fracture spots in sputtered or evaporated metal which covers the steps. In the fabrication of self-aligned gate IGFETs, where the gate material acts as a mask against either etching or ion implantation, holes in the step metal will allow regions under the nominal gate to be doped during the source-drain doping. The slope of an etched step can be controlled by fabricating a double layer in which the top layer etches faster than the bulk. The specification describes the use of the enhanced etch rate of ion bombarded SiO2 to generate controlled tapers on window openings.

Abstract translation: 在SiO2蚀刻期间，当氧化物表面蚀刻速率大于体蚀刻速率并且光致抗蚀剂牢固地粘附到表面时，将形成近垂直的壁或尖点。 这将在溅射或蒸发的金属中产生潜在的断裂点，覆盖了这些步骤。 在自对准栅极IGFET的制造中，其中栅极材料充当蚀刻或离子注入的掩模，阶跃金属中的空穴将允许在源极 - 漏极掺杂期间在标称栅极之下的区域被掺杂。