SPACER FORMATION PROCESS WITH FLAT TOP PROFILE
    2.
    发明申请
    SPACER FORMATION PROCESS WITH FLAT TOP PROFILE 审中-公开
    具有平面顶部轮廓的间隙形成过程

    公开(公告)号:US20160307772A1

    公开(公告)日:2016-10-20

    申请号:US14968509

    申请日:2015-12-14

    Abstract: Embodiments described herein relate to methods for etching a substrate. Patterning processes, such as double patterning and quadruple patterning processes, may benefit from the embodiments described herein which include performing an inert plasma treatment to implant ions into a spacer material, performing an etching process on an implanted region of the spacer material, and repeating the inert plasma treatment and the etching process to form a predominantly flat top spacer profile. The inert plasma treatment process may be a biased process and the etching process may be an unbiased process. Various processing parameters, such as pressure, may be controlled to influence a desired spacer profile.

    Abstract translation: 本文所述的实施例涉及用于蚀刻衬底的方法。 图案化处理,例如双重图案化和四重图案化处理,可以受益于本文所述的实施例,其包括进行惰性等离子体处理以将离子注入到间隔物材料中,对间隔物材料的注入区域进行蚀刻处理,并重复 惰性等离子体处理和蚀刻工艺以形成主要平坦的顶部间隔物轮廓。 惰性等离子体处理工艺可以是偏压工艺,并且蚀刻工艺可以是无偏的工艺。 可以控制诸如压力的各种处理参数以影响期望的间隔物轮廓。

    METHODS FOR SILICON RECESS STRUCTURES IN A SUBSTRATE BY UTILIZING A DOPING LAYER
    3.
    发明申请
    METHODS FOR SILICON RECESS STRUCTURES IN A SUBSTRATE BY UTILIZING A DOPING LAYER 有权
    通过使用掺杂层对基底中的硅回收结构的方法

    公开(公告)号:US20150118822A1

    公开(公告)日:2015-04-30

    申请号:US14068312

    申请日:2013-10-31

    Abstract: Embodiments of the present invention provide a methods for forming silicon recess structures in a substrate with good process control, particularly suitable for manufacturing three dimensional (3D) stacking of fin field effect transistor (FinFET) for semiconductor chips. In one embodiment, a method of forming recess structures in a substrate includes etching a first portion of a substrate defined by a second portion formed in the substrate until a doping layer formed in the substrate is exposed.

    Abstract translation: 本发明的实施例提供了一种用于在具有良好的工艺控制的衬底中形成硅凹陷结构的方法,特别适用于制造用于半导体芯片的鳍式场效应晶体管(FinFET)的三维(3D)堆叠。 在一个实施例中,在衬底中形成凹陷结构的方法包括蚀刻由形成在衬底中的第二部分限定的衬底的第一部分,直到形成在衬底中的掺杂层露出。

    METHODS FOR BOTTOM UP FIN STRUCTURE FORMATION

    公开(公告)号:US20190252187A1

    公开(公告)日:2019-08-15

    申请号:US16259585

    申请日:2019-01-28

    Abstract: Embodiments described herein relate to substrate processing methods. The methods include forming a patterned hardmask material on a substrate, forming first mandrel structures on exposed regions of the substrate, and depositing a gap fill material on the substrate over the hardmask material and the first mandrel structures. The first mandrel structures are removed to expose second regions of the substrate and form second mandrel structures comprising the hardmask material and the gap fill material. Fin structures are deposited on the substrate using the second mandrel structures as a mask.

    SELF ALIGNED REPLACEMENT FIN FORMATION
    6.
    发明申请
    SELF ALIGNED REPLACEMENT FIN FORMATION 有权
    自我对齐替代费用形成

    公开(公告)号:US20160079126A1

    公开(公告)日:2016-03-17

    申请号:US14864389

    申请日:2015-09-24

    Abstract: Methods and apparatus for forming FinFET structures are provided. Selective etching and deposition processes described herein may provide for FinFET manufacturing without the utilization of multiple patterning processes. Embodiments described herein also provide for fin material manufacturing methods for transitioning from silicon to III-V materials while maintaining acceptable crystal lattice orientations of the various materials utilized. Further embodiments provide etching apparatus which may be utilized to perform the methods described herein.

    Abstract translation: 提供了用于形成FinFET结构的方法和装置。 本文所述的选择性蚀刻和沉积工艺可以提供FinFET制造而不利用多个图案化工艺。 本文描述的实施例还提供了用于从硅转变为III-V材料的翅片材料制造方法,同时保持所使用的各种材料的可接受的晶格取向。 另外的实施例提供可用于执行本文所述方法的蚀刻装置。

    FIN STRUCTURE FORMATION BY SELECTIVE ETCHING
    9.
    发明申请
    FIN STRUCTURE FORMATION BY SELECTIVE ETCHING 有权
    通过选择性蚀刻形成的FIN结构

    公开(公告)号:US20160099178A1

    公开(公告)日:2016-04-07

    申请号:US14875013

    申请日:2015-10-05

    Abstract: Methods and apparatus for forming FinFET structures are provided. Selective etching and deposition processes described herein may provide for FinFET manufacturing without the utilization of multiple patterning processes. Embodiments described herein also provide for fin material manufacturing methods for transitioning from silicon to III-V materials while maintaining acceptable crystal lattice orientations of the various materials utilized. Further embodiments provide etching apparatus which may be utilized to perform the methods described herein.

    Abstract translation: 提供了用于形成FinFET结构的方法和装置。 本文所述的选择性蚀刻和沉积工艺可以提供FinFET制造而不利用多个图案化工艺。 本文描述的实施例还提供了用于从硅转变为III-V材料的翅片材料制造方法,同时保持所使用的各种材料的可接受的晶格取向。 另外的实施例提供可用于执行本文所述方法的蚀刻装置。

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