公开(公告)号：US20070241443A1

公开(公告)日：2007-10-18

申请号：US11403626

申请日：2006-04-13

申请人： Adrian Ong ,  Dong Jeong

发明人： Adrian Ong ,  Dong Jeong

IPC分类号： H01L23/48

CPC分类号： H01L23/50 ,  H01L21/485 ,  H01L23/5382 ,  H01L2924/0002 ,  H01L2924/00

摘要： Methods, systems, and apparatus for reducing power consumption or signal distortions in a semiconductor device package. The semiconductor device package includes a semiconductor device, a first electric path, a second electric path, and an isolation element in the first electric path. The second electric path is electrically connected to the first electric path and a functional unit of the device. The isolation element separates an isolated portion in the first electric path from the second electric path, where the isolation element is configured to reduce current in the isolated portion when a signal is passing through the second electric path.

摘要翻译： 用于减少半导体器件封装中的功率消耗或信号失真的方法，系统和装置。 半导体器件封装包括第一电路中的半导体器件，第一电路，第二电路和隔离元件。 第二电路与第一电路电连接，该装置的功能单元。 隔离元件将第一电路中的隔离部分与第二电路分离，其中隔离元件被配置为当信号通过第二电通路时减小隔离部分中的电流。

公开(公告)号：US08750018B2

公开(公告)日：2014-06-10

申请号：US13488432

申请日：2012-06-04

申请人： YongSik Youn ,  Adrian Ong ,  Sooho Cha ,  Chan-kyung Kim

发明人： YongSik Youn ,  Adrian Ong ,  Sooho Cha ,  Chan-kyung Kim

IPC分类号： G11C11/00

CPC分类号： G11C7/062 ,  G11C7/12 ,  G11C11/1653 ,  G11C11/1673 ,  G11C11/1675 ,  G11C13/0002 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/004 ,  G11C2013/0042 ,  G11C2207/063

摘要： Example embodiments include a resistive type memory current sense amplifier circuit including differential output terminals, first and second input terminals, pre-charge transistors, and current modulating transistors coupled directly to the pre-charge transistors. The pre-charge configuration provides high peak currents to charge the bit line and reference line during a “ready” or “pre-charge” stage of operation of the current sense amplifier circuit. The current modulating transistors are configured to operate in a saturation region mode during at least a “set” or “amplification” stage. The current modulating transistors continuously average a bit line current and a reference line current during the “set” or “amplification” stage, thereby improving noise immunity of the circuit. During a “go” or “latch” stage of operation, a logical value “0” or “1” is latched at the differential output terminals based on positive feedback of a latch circuit.

摘要翻译： 示例实施例包括包括差分输出端子，直接耦合到预充电晶体管的第一和第二输入端子，预充电晶体管和电流调制晶体管的电阻型存储电流读出放大器电路。 预充电配置提供高峰值电流，以在电流检测放大器电路的“准备”或“预充电”阶段期间为位线和参考线充电。 电流调制晶体管被配置为在至少“设置”或“放大”阶段期间以饱和区域模式工作。 电流调制晶体管在“设置”或“放大”级期间连续平均位线电流和参考线电流，从而提高电路的抗噪声能力。 在“去”或“锁存”操作阶段期间，基于锁存电路的正反馈，在差分输出端子处锁存逻辑值“0”或“1”。

公开(公告)号：US20130027006A1

公开(公告)日：2013-01-31

申请号：US13193311

申请日：2011-07-28

申请人： Rendon Holloway ,  Adrian Ong ,  Howard Hou

发明人： Rendon Holloway ,  Adrian Ong ,  Howard Hou

IPC分类号： G05F1/10 ,  G05F1/00

CPC分类号： H02M3/158 ,  H02J1/02

摘要： A boost power converter system according to one embodiment includes an input voltage high-side node; an inductor coupled to the input voltage high-side node at a first terminal of the inductor; a power switch coupled to the inductor at a second terminal of the inductor; a drive circuit configured to control the power switch such that the boost power converter system operates in a discontinuous conduction mode when a load current drops below a critical conduction threshold; and a damping switch configured to enable current flow from the power switch at the second terminal of the inductor to the input voltage high-side node, wherein the damping switch is closed when the power switch is open and the damping switch is opened when the power switch is closed.

摘要翻译： 根据一个实施例的升压功率转换器系统包括输入电压高侧节点; 电感器，其耦合到电感器的第一端处的输入电压高侧节点; 在所述电感器的第二端子处耦合到所述电感器的功率开关; 驱动电路，被配置为控制所述功率开关，使得当负载电流下降到临界导通阈值以下时，所述升压功率转换器系统工作在不连续导通模式; 以及阻尼开关，其构造成使得能够从电感器的第二端子处的电力开关到输入电压高侧节点的电流流动，其中当电源开关断开时阻尼开关闭合，并且阻尼开关在电力 开关关闭。

公开(公告)号：US20070067687A1

公开(公告)日：2007-03-22

申请号：US11552944

申请日：2006-10-25

申请人： Adrian Ong

发明人： Adrian Ong

IPC分类号： G01R31/28

CPC分类号： G01R31/31928 ,  G01R31/31905 ,  G01R31/31922 ,  G01R31/31926 ,  G06F11/263 ,  G11C29/14 ,  G11C29/56 ,  G11C29/56012 ,  G11C2029/5602

摘要： Systems and methods of testing integrated circuits are disclosed. The systems include a test module configured to operate between automated testing equipment and an integrated circuit to be tested. The testing interface is configured to test time sensitive parameters of the integrated circuit. The testing interface includes components for generating addresses, commands, and test data to be conveyed to the integrated circuit as well as a clock adjustment component. By adjusting the clock synchronization controlling the test signals to be conveyed to the integrated circuit, set-up time and hold time can be tested. The systems are configured to test set-up time and hold time of individual data channels, for example, an individual address line of the integrated circuit.

摘要翻译： 公开了测试集成电路的系统和方法。 这些系统包括配置成在自动测试设备和要测试的集成电路之间运行的测试模块。 测试界面配置为测试集成电路的时间敏感参数。 测试接口包括用于产生要传送到集成电路的地址，命令和测试数据以及时钟调整组件的组件。 通过调整控制要传送到集成电路的测试信号的时钟同步，可以测试设置时间和保持时间。 这些系统被配置为测试各个数据信道（例如，集成电路的单独地址线）的建立时间和保持时间。

公开(公告)号：US20050024977A1

公开(公告)日：2005-02-03

申请号：US10877687

申请日：2004-06-25

申请人： Adrian Ong

发明人： Adrian Ong

IPC分类号： G11C29/48 ,  G11C8/02

CPC分类号： G11C29/1201 ,  G11C29/48 ,  G11C2207/104 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49175 ,  H01L2924/00014

摘要： A semiconductor memory chip is provided for packaging along with a system chip in a single semiconductor package having a plurality of external connectors. The memory chip includes a memory storage array for storing data. A plurality of data buffers is provided for writing or reading data between said memory storage array and the system chip within the single semiconductor package. A first power level may be used for each of the plurality of data buffers. At least one test buffer is directly connected to certain of said plurality of external connectors for supporting testing of said memory chip within the single semiconductor package by external test equipment. A second power level may be used for the test buffer.

摘要翻译： 提供半导体存储器芯片，用于与具有多个外部连接器的单个半导体封装中的系统芯片一起封装。 存储器芯片包括用于存储数据的存储器存储阵列。 提供多个数据缓冲器用于在单个半导体封装内的所述存储器阵列和系统芯片之间写入或读取数据。 第一功率电平可以用于多个数据缓冲器中的每一个。 至少一个测试缓冲器直接连接到所述多个外部连接器中的某些，用于通过外部测试设备支持单个半导体封装内的所述存储器芯片的测试。 第二功率电平可用于测试缓冲器。

公开(公告)号：US5293342A

公开(公告)日：1994-03-08

申请号：US993929

申请日：1992-12-17

申请人： Stephen L. Casper ,  Adrian Ong ,  Paul S. Zagar

发明人： Stephen L. Casper ,  Adrian Ong ,  Paul S. Zagar

IPC分类号： G11C8/08 ,  G11C11/408 ,  G11C7/00

CPC分类号： G11C8/08 ,  G11C11/4085

摘要： The invention is an automatic precharge circuit featuring precharge devices each of which is interposed between a high voltage node, connectable to a supply potential, and a serial node. The precharge devices are gated automatically by a primary predecode signal of a decode portion of the row decoder. Power is conserved since the serial nodes are passively pulled to the supply potential through the precharge devices. The invention increases speed and provides error free wordline selection.

摘要翻译： 本发明是一种自动预充电电路，其特征在于预充电装置各自插入在可连接到电源电位的高压节点和串联节点之间。 预充电装置由行解码器的解码部分的主要预解码信号自动选通。 功率节省，因为串行节点被动地通过预充电器件拉到电源电位。 本发明提高了速度并提供了无错误的字线选择。

公开(公告)号：US20130212431A1

公开(公告)日：2013-08-15

申请号：US13691639

申请日：2012-11-30

申请人： Adrian Ong

发明人： Adrian Ong

IPC分类号： G06F11/07 ,  G06F12/00 ,  G11C11/16

CPC分类号： G06F15/167 ,  G06F3/0601 ,  G06F11/0751 ,  G06F11/0793 ,  G06F11/1008 ,  G06F11/1076 ,  G06F12/00 ,  G06F21/00 ,  G11C11/16 ,  G11C11/1677 ,  G11C11/1695 ,  G11C13/0002

摘要： A smart memory system preferably includes a memory including one or more memory chips, and a processor including one or more memory processor chips. The processor may include a common address/data/control memory bus that is configured to provide an asynchronous handshaking interface between the memory array and the memory processor. The processor can offload error data from the memory chip for analysis, and can store poor retention bit address information for memory refreshing in a non-volatile error retention memory. Program logic can also be included for memory address re-configuration. Power management logic can also be included, which may have a process-voltage-temperature compensation voltage generator for providing stable and constant read currents. An asynchronous handshaking interface is provided between the memory array and the memory processor. Write error tagging and write verification circuits can also be included.

摘要翻译： 智能存储器系统优选地包括包括一个或多个存储器芯片的存储器和包括一个或多个存储器处理器芯片的处理器。 处理器可以包括公共地址/数据/控制存储器总线，其被配置为在存储器阵列和存储器处理器之间提供异步握手接口。 处理器可以从内存芯片卸载错误数据进行分析，并且可以在非易失性错误保留存储器中存储用于内存刷新的差的保留位地址信息。 还可以包括程序逻辑用于存储器地址重新配置。 还可以包括电源管理逻辑，其可以具有用于提供稳定且恒定的读取电流的过程电压 - 温度补偿电压发生器。 在存储器阵列和存储器处理器之间提供异步握手接口。 也可以包括写入错误标记和写入验证电路。

公开(公告)号：US20050289428A1

公开(公告)日：2005-12-29

申请号：US11207518

申请日：2005-08-19

申请人： Adrian Ong

发明人： Adrian Ong

IPC分类号： G01R31/28 ,  G01R31/3185 ,  G01R31/319 ,  G06F11/00

CPC分类号： G01R31/31926 ,  G01R31/31723 ,  G01R31/318505 ,  G01R31/318511 ,  G01R31/31905 ,  G01R31/31917

摘要： In one embodiment, the present invention provides a platform of hardware and/or software that enables the complete access and reliable testing of multiple integrated circuit (IC) devices within a package. This platform may include a testing component (e.g., test circuits, test pads, shared pads, etc.), one or more probe cards and related hardware, wafer probe programs, load board and related hardware of external test equipment, and software and routines for final test programs.

摘要翻译： 在一个实施例中，本发明提供了一种硬件和/或软件平台，其能够对封装内的多个集成电路（IC）器件进行完全访问和可靠测试。 该平台可以包括测试部件（例如，测试电路，测试焊盘，共享焊盘等），一个或多个探针卡和相关硬件，晶片探针程序，负载板和外部测试设备的相关硬件以及软件和例程 用于最终测试程序。

公开(公告)号：US20050005208A1

公开(公告)日：2005-01-06

申请号：US09777036

申请日：2001-02-05

申请人： Douglas Cutter ,  Adrian Ong ,  Fan Ho ,  Kurt Beigel ,  Brett Debenham ,  Dien Luong ,  Kim Pierce ,  Patrick Mullarkey

发明人： Douglas Cutter ,  Adrian Ong ,  Fan Ho ,  Kurt Beigel ,  Brett Debenham ,  Dien Luong ,  Kim Pierce ,  Patrick Mullarkey

IPC分类号： G11C17/18 ,  G01R31/28

CPC分类号： G11C17/18

摘要： Method and apparatus are disclosed for checking the resistance of antifuse elements in an integrated circuit. A voltage based on the resistance of an antifuse element is compared to a voltage based on a known resistance, and an output signal is generated whose binary value indicates whether the resistance of the antifuse element is higher or lower than the known value of resistance. The method and apparatus are useful in verifying the programming of antifuse elements.

摘要翻译： 公开了用于检查集成电路中的反熔丝元件的电阻的方法和装置。 将基于反熔丝元件的电阻的电压与基于已知电阻的电压进行比较，并且生成其二进制值表示反熔丝元件的电阻是否高于或低于已知电阻值的输出信号。 该方法和装置在验证反熔丝元件的编程方面是有用的。

公开(公告)号：US5999480A

公开(公告)日：1999-12-07

申请号：US167259

申请日：1998-10-06

申请人： Adrian Ong ,  Paul S. Zagar ,  Troy Manning ,  Brent Keeth ,  Ken Waller

发明人： Adrian Ong ,  Paul S. Zagar ,  Troy Manning ,  Brent Keeth ,  Ken Waller

IPC分类号： G11C5/02 ,  G11C7/10 ,  G11C11/4096 ,  G11C29/00 ,  G11C29/36 ,  G11C8/00

CPC分类号： G11C29/785 ,  G11C11/4096 ,  G11C29/80 ,  G11C29/88 ,  G11C5/025 ,  G11C7/10 ,  G11C29/36

摘要： A semiconductor dynamic random-access memory (DRAM) device embodying numerous features that collectively and/or individually prove beneficial and advantageous with regard to such considerations as density, power consumption, speed, and redundancyis disclosed. The device is a 64 Mbit DRAM comprising eight substantially identical 8 Mbit partial array blocks (PABs), each pair of PABs comprising a 16 Mbit quadrant of the device. Between the top two quadrants and between the bottom two quadrants are column blocks containing I/O read/write circuitry, column redundancy fuses, and column decode circuitry. Column select lines originate from the column blocks and extend right and left across the width of each quadrant. Each PAB comprises eight substantially identical 1Mbit sub-array blocks (SABs). Associated with each SAB are a plurality of local row decoder circuits functioning to receive partially decoded row addresses from a column predecoder circuit and generating local row addresses supplied to the SAB with which they are associated. A hierarchical data path is provided wherein a plurality of multiplexers are distributed throughout each SAB, these multiplexers functioning to selectively couple sense amplifier output signals to local data I/O lines associated with each SAB. In one embodiment, the data path multiplexers are physically disposed within gaps defined by adjacent ones of the local row address decoders distributed throughout each SAB.

摘要翻译： 一种体现许多特征的半导体动态随机存取存储器（DRAM）装置，其集合和/或单独证明在所公开的诸如密度，功耗，速度和冗余度之类的考虑方面是有益和有利的。 该器件是包括八个基本上相同的8兆位部分阵列块（PAB）的64Mbit DRAM，每对PAB包括该器件的16Mb象限。 顶部两个象限之间和底部两个象限之间是包含I / O读/写电路，列冗余保险丝和列解码电路的列块。 列选择线来自列块，并在每个象限的宽度上左右延伸。 每个PAB包括八个基本相同的1M位子阵列块（SAB）。 与每个SAB相关联的是多个本地行解码器电路，用于从列预解码器电路接收部分解码的行地址，并产生提供给与它们相关联的SAB的本地行地址。 提供了分层数据路径，其中多个复用器分布在每个SAB中，这些多路复用器用于选择性地将感测放大器输出信号耦合到与每个SAB相关联的本地数据I / O线。 在一个实施例中，数据路径多路复用器物理地布置在分布在每个SAB中的相邻的本地行地址解码器限定的间隙内。