公开(公告)号：US09984976B2

公开(公告)日：2018-05-29

申请号：US15041454

申请日：2016-02-11

申请人： APPLIED MATERIALS, INC.

发明人： Yana Cheng ,  Yong Cao ,  Srinivas Guggilla ,  Sree Rangasai Kesapragada ,  Xianmin Tang ,  Deenesh Padhi

IPC分类号： H01L23/48 ,  H01L23/532 ,  H01L21/768

CPC分类号： H01L23/53238 ,  C23C14/0036 ,  C23C14/0676 ,  C23C14/352 ,  H01J37/32504 ,  H01J37/3408 ,  H01J37/3455 ,  H01L21/02145 ,  H01L21/02266 ,  H01L21/76802 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/53223 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295

摘要： Interconnect structures and methods of formation of such interconnect structures are provided herein. In some embodiments, a method of forming an interconnect includes: depositing a silicon-aluminum oxynitride (SiAlON) layer atop a first layer of a substrate, wherein the first layer comprises a first feature filled with a first conductive material; depositing a dielectric layer over the silicon-aluminum oxynitride (SiAlON) layer; and forming a second feature in the dielectric layer and the silicon-aluminum oxynitride (SiAlON) layer to expose the first conductive material.

公开(公告)号：US09646876B2

公开(公告)日：2017-05-09

申请号：US14634512

申请日：2015-02-27

申请人： Applied Materials, Inc.

发明人： Deenesh Padhi ,  Srinivas Guggilla ,  Alexandros T. Demos ,  Bhaskar Kumar ,  He Ren ,  Priyanka Dash

IPC分类号： H01L21/44 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532

CPC分类号： H01L21/76813 ,  H01L21/02458 ,  H01L21/76808 ,  H01L21/76831 ,  H01L21/76862 ,  H01L23/53295

摘要： A method of forming features in a dielectric layer is described. A via, trench or a dual-damascene structure may be present in the dielectric layer prior to depositing a conformal aluminum nitride layer. The conformal aluminum nitride layer is configured to serve as a barrier to prevent diffusion across the barrier. The methods of forming the aluminum nitride layer involve the alternating exposure to two precursor treatments (like ALD) to achieve high conformality. The high conformality of the aluminum nitride barrier layer enables the thickness to be reduced and the effective conductivity of the subsequent gapfill metal layer to be increased.

公开(公告)号：US11527408B2

公开(公告)日：2022-12-13

申请号：US16867095

申请日：2020-05-05

申请人： Applied Materials, Inc.

发明人： Tzu-shun Yang ,  Rui Cheng ,  Karthik Janakiraman ,  Zubin Huang ,  Diwakar Kedlaya ,  Meenakshi Gupta ,  Srinivas Guggilla ,  Yung-chen Lin ,  Hidetaka Oshio ,  Chao Li ,  Gene Lee

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/3213

摘要： The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a first mandrel layer on a material layer disposed on a substrate. A first spacer layer is conformally formed on sidewalls of the first mandrel layer, wherein the first spacer layer comprises a doped silicon material. The first mandrel layer is selectively removed while keeping the first spacer layer. A second spacer layer is conformally formed on sidewalls of the first spacer layer and selectively removing the first spacer layer while keeping the second spacer layer.

公开(公告)号：US10002834B2

公开(公告)日：2018-06-19

申请号：US14711135

申请日：2015-05-13

申请人： Applied Materials, Inc.

发明人： Mehul B. Naik ,  Paul F. Ma ,  Tae Hong Ha ,  Srinivas Guggilla

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L23/532 ,  H01L21/285

CPC分类号： H01L23/53238 ,  H01L21/28556 ,  H01L21/76846

摘要： A method and apparatus for forming an interconnect on a substrate is provided. A protective layer is formed on the substrate and in a via formed on the substrate wherein the protective layer is resistant to a halogen containing material. A barrier layer is formed on top of the protective layer. The barrier layer comprises a halogen containing material. A metal layer is deposited over the barrier layer. In another embodiment, the protective layer is selectively deposited in the via.

公开(公告)号：US11315787B2

公开(公告)日：2022-04-26

申请号：US16821759

申请日：2020-03-17

申请人： Applied Materials, Inc.

发明人： Tzu-shun Yang ,  Rui Cheng ,  Karthik Janakiraman ,  Zubin Huang ,  Diwakar Kedlaya ,  Meenakshi Gupta ,  Srinivas Guggilla ,  Yung-chen Lin ,  Hidetaka Oshio ,  Chao Li ,  Gene Lee

IPC分类号： H01L21/033 ,  H01L21/311 ,  H01L21/3213

摘要： The present disclosure provides forming nanostructures utilizing multiple patterning process with good profile control and feature transfer integrity. In one embodiment, a method for forming features on a substrate includes forming a mandrel layer on a substrate, conformally forming a spacer layer on the mandrel layer, wherein the spacer layer is a doped silicon material, and patterning the spacer layer. In another embodiment, a method for forming features on a substrate includes conformally forming a spacer layer on a mandrel layer on a substrate, wherein the spacer layer is a doped silicon material, selectively removing a portion of the spacer layer using a first gas mixture, and selectively removing the mandrel layer using a second gas mixture different from the first gas mixture.

公开(公告)号：US10700087B2

公开(公告)日：2020-06-30

申请号：US16151467

申请日：2018-10-04

申请人： Applied Materials, Inc.

发明人： Xinhai Han ,  Deenesh Padhi ,  Er-Xuan Ping ,  Srinivas Guggilla

IPC分类号： H01L21/76 ,  H01L27/11582 ,  H01L21/311 ,  H01L21/02 ,  H01L27/1157

摘要： Embodiments described herein relate to methods and materials for fabricating semiconductor devices, such as memory devices and the like. In one embodiment, a memory layer stack includes materials having differing etch rates in which one material is selectively removed to form an airgap in the device structure. In another embodiment, silicon containing materials of a memory layer stack are doped or fabricated as a silicide material. In another embodiment, a silicon nitride material is utilized as an interfacial layer between oxide containing and silicon containing layers of a memory layer stack.

公开(公告)号：US10468238B2

公开(公告)日：2019-11-05

申请号：US15240927

申请日：2016-08-18

申请人： APPLIED MATERIALS, INC.

发明人： Anantha K. Subramani ,  Hanbing Wu ,  Wei W. Wang ,  Ashish Goel ,  Srinivas Guggilla ,  Lavinia Nistor

IPC分类号： H01J37/34 ,  C23C14/34

摘要： Embodiments of a method and apparatus for co-sputtering multiple target materials are provided herein. In some embodiments, a process chamber including a substrate support to support a substrate; a plurality of cathodes coupled to a carrier and having a corresponding plurality of targets to be sputtered onto the substrate; and a process shield coupled to the carrier and extending between adjacent pairs of the plurality of targets.

公开(公告)号：US20160254181A1

公开(公告)日：2016-09-01

申请号：US14634512

申请日：2015-02-27

申请人： Applied Materials, Inc.

发明人： Deenesh Padhi ,  Srinivas Guggilla ,  Alexandros T. Demos ,  Bhaskar Kumar ,  He Ren ,  Priyanka Dash

IPC分类号： H01L21/768 ,  H01L21/02

CPC分类号： H01L21/76813 ,  H01L21/02458 ,  H01L21/76808 ,  H01L21/76831 ,  H01L21/76862 ,  H01L23/53295

摘要： A method of forming features in a dielectric layer is described. A via, trench or a dual-damascene structure may be present in the dielectric layer prior to depositing a conformal aluminum nitride layer. The conformal aluminum nitride layer is configured to serve as a barrier to prevent diffusion across the barrier. The methods of forming the aluminum nitride layer involve the alternating exposure to two precursor treatments (like ALD) to achieve high conformality. The high conformality of the aluminum nitride barrier layer enables the thickness to be reduced and the effective conductivity of the subsequent gapfill metal layer to be increased.

摘要翻译： 描述了在电介质层中形成特征的方法。 通孔，沟槽或双镶嵌结构可能在沉积保形氮化铝层之前存在于电介质层中。 保形氮化铝层被配置为用作屏障以防止穿过屏障的扩散。 形成氮化铝层的方法涉及交替暴露于两种前体处理（如ALD）以实现高共形性。 氮化铝阻挡层的高共形度使得能够减小厚度，并且随后的间隙填充金属层的有效导电性增加。

公开(公告)号：US20240266185A1

公开(公告)日：2024-08-08

申请号：US18106697

申请日：2023-02-07

申请人： Applied Materials, Inc.

发明人： Han Wang ,  Yu Yang ,  Jing Zhang ,  Aykut Aydin ,  Guoqing Li ,  Guangyan Zhong ,  Rui Cheng ,  Gene H. Lee ,  Srinivas Guggilla ,  Sinae Heo ,  Eswaranand Venkatasubramanian ,  Abhijit Basu Mallick ,  Karthik Janakiraman

IPC分类号： H01L21/311 ,  H01L21/033

CPC分类号： H01L21/31144 ,  H01L21/0332

摘要： Exemplary semiconductor processing methods may include depositing a metal-doped boron-containing material on a substrate disposed within a processing region of a semiconductor processing chamber. The metal-doped boron-containing material may include a metal dopant comprising tungsten. The substrate may include a silicon-containing material. The methods may include depositing one or more additional materials over the metal-doped boron-containing material. The one or more additional materials may include a patterned photoresist material. The methods may include transferring a pattern from the patterned photoresist material to the metal-doped boron-containing material. The methods may include etching the metal-doped boron-containing material with a chlorine-containing precursor. The methods may include etching the silicon-containing material with a fluorine-containing precursor. The metal dopant may enhance an etch rate of the silicon-containing material. The methods may include removing the metal-doped boron-containing material from the substrate with a halogen-containing precursor.

公开(公告)号：US20240249953A1

公开(公告)日：2024-07-25

申请号：US18098791

申请日：2023-01-19

申请人： Applied Materials, Inc.

发明人： Yeonju Kwak ,  Jeong Hwan Kim ,  Qian Fu ,  Siyu Zhu ,  Hang Yu ,  Srinivas Guggilla

IPC分类号： H01L21/311 ,  H01J37/32

CPC分类号： H01L21/31122 ,  H01J37/32816 ,  H01L21/31144 ,  H10B69/00

摘要： Exemplary methods of semiconductor processing may include providing a fluorine-containing precursor to a processing region of a semiconductor processing chamber. A substrate may be housed within the processing region. The substrate may include a boron-containing material overlying a carbon-containing material. The methods may include generating plasma effluents of the fluorine-containing precursor. The methods may include contacting the substrate with the plasma effluents of the fluorine-containing precursor. The methods may include removing the boron-containing material from the substrate.