公开(公告)号：US11830725B2

公开(公告)日：2023-11-28

申请号：US17153450

申请日：2021-01-20

Applicant: Applied Materials, Inc.

Inventor： Naomi Yoshida ,  He Ren ,  Hao Jiang ,  Chenfei Shen ,  Chi-Chou Lin ,  Hao Chen ,  Xuesong Lu ,  Mehul B. Naik

IPC: H01L21/02 ,  H01L21/28 ,  B08B5/02 ,  H01L29/66 ,  H01L21/3205

CPC classification number: H01L21/02057 ,  B08B5/02 ,  H01L21/28026 ,  H01L21/32051 ,  H01L29/66795

Abstract: Embodiments of the present disclosure generally relate to methods of cleaning a structure and methods of depositing a capping layer in a structure. The method of cleaning a structure includes suppling a cleaning gas, including a first gas including nitrogen (N) and a second gas including fluorine (F), to a bottom surface of a structure. The cleaning gas removes unwanted metal oxide and etch residue from the bottom surface of the structure. The method of depositing a capping layer includes depositing the capping layer over the bottom surface of the structure. The methods described herein reduce the amount of unwanted metal oxides and residue, which improves adhesion of deposited capping layers.

公开(公告)号：US10930472B2

公开(公告)日：2021-02-23

申请号：US16250763

申请日：2019-01-17

Applicant: Applied Materials, Inc.

Inventor： Bencherki Mebarki ,  Annamalai Lakshmanan ,  Kaushal K. Singh ,  Andrew Cockburn ,  Ludovic Godet ,  Paul F. Ma ,  Mehul B. Naik

IPC: H01J37/32 ,  C23C16/42 ,  C23C16/56 ,  H01L21/285 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/268

Abstract: Methods and apparatus for forming a metal silicide as nanowires for back-end interconnection structures for semiconductor applications are provided. In one embodiment, the method includes forming a metal silicide layer on a substrate by a chemical vapor deposition process or a physical vapor deposition process, thermal treating the metal silicide layer in a processing chamber, applying a microwave power in the processing chamber while thermal treating the metal silicide layer; and maintaining a substrate temperature less than 400 degrees Celsius while thermal treating the metal silicide layer. In another embodiment, a method includes supplying a deposition gas mixture including at least a metal containing precursor and a reacting gas on a surface of a substrate, forming a plasma in the presence of the deposition gas mixture by exposure to microwave power, exposing the plasma to light radiation, and forming a metal silicide layer on the substrate from the deposition gas.

公开(公告)号：US10593592B2

公开(公告)日：2020-03-17

申请号：US14975028

申请日：2015-12-18

Applicant: Applied Materials, Inc.

Inventor： Bencherki Mebarki ,  Annamalai Lakshmanan ,  Kaushal K. Singh ,  Paul F. Ma ,  Mehul B. Naik ,  Andrew Cockburn ,  Ludovic Godet

IPC: H01L21/768 ,  H01L21/285 ,  H01L23/532 ,  H01L21/3205

Abstract: Methods and apparatus for forming a metal silicide as nanowires for back-end interconnection structures for semiconductor applications are provided. In one embodiment, the method includes forming a metal silicide stack comprising as plurality of metal silicide layers on a substrate by a chemical vapor deposition process or a physical vapor deposition process, thermal treating the metal silicide stack in a processing chamber, applying a microwave power in the processing chamber while thermal treating the metal silicide layer; and maintaining a substrate temperature less than 400 degrees Celsius while thermal treating the metal silicide layer.

公开(公告)号：US09613859B2

公开(公告)日：2017-04-04

申请号：US14975231

申请日：2015-12-18

Applicant: Applied Materials, Inc.

Inventor： Annamalai Lakshmanan ,  Bencherki Mebarki ,  Kaushal K. Singh ,  Paul F. Ma ,  Mehul B. Naik ,  Andrew Cockburn ,  Ludovic Godet

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/3205 ,  H01L23/532

CPC classification number: H01L21/76879 ,  H01L21/28518 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/32053 ,  H01L21/76802 ,  H01L21/76876 ,  H01L21/76886 ,  H01L21/76889 ,  H01L23/53257 ,  H01L23/53271 ,  H01L2221/1094

Abstract: Methods for direct deposition of a metal silicide nanowire for back-end interconnection structures for semiconductor applications are provided. In one embodiment, the method includes positioning a substrate in a processing region of a process chamber, the substrate having a first surface comprising a non-dielectric material; and a dielectric layer formed on the first surface. An opening is formed in the dielectric layer, the opening exposing at least a portion of the first surface, the opening having sidewalls. A metal silicide seed is deposited in the opening using a PVD process, wherein the PVD process is performed with either no bias or a bias which creates deposition on the sidewall which is less than 1% of the deposition on the first surface. A metal silicide layer is then selectively deposited on the metal silicide seed using a metal-silicon organic precursor, creating the metal silicide nanowire.

公开(公告)号：US09337051B2

公开(公告)日：2016-05-10

申请号：US14799374

申请日：2015-07-14

Applicant: Applied Materials, Inc.

Inventor： Bencherki Mebarki ,  Bok Hoen Kim ,  Deenesh Padhi ,  Li Yan Miao ,  Pramit Manna ,  Christopher Dennis Bencher ,  Mehul B. Naik ,  Huixiong Dai ,  Christopher S. Ngai ,  Daniel Lee Diehl

IPC: H01L21/00 ,  H01L21/308 ,  H01L21/311 ,  H01L21/02 ,  H01L21/027

CPC classification number: H01L21/3088 ,  H01L21/02115 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144

Abstract: Embodiments of the disclosure generally provide a method of forming a reduced dimension pattern in a hardmask that is optically matched to an overlying photoresist layer. The method generally comprises of application of a dimension shrinking conformal carbon layer over the field region, sidewalls, and bottom portion of the patterned photoresist and the underlying hardmask at temperatures below the decomposition temperature of the photoresist. The methods and embodiments herein further involve removal of the conformal carbon layer from the bottom portion of the patterned photoresist and the hardmask by an etch process to expose the hardmask, etching the exposed hardmask substrate at the bottom portion, followed by the simultaneous removal of the conformal carbon layer, the photoresist, and other carbonaceous components. A hardmask with reduced dimension features for further pattern transfer is thus yielded.

Abstract translation: 本公开的实施例通常提供在与上覆光致抗蚀剂层光学匹配的硬掩模中形成减小尺寸图案的方法。 该方法通常包括在低于光致抗蚀剂的分解温度的温度下，在图案化的光致抗蚀剂和下面的硬掩模的场区域，侧壁和底部上施加尺寸收缩的保形碳层。 本文的方法和实施例还涉及通过蚀刻工艺从图案化的光致抗蚀剂和硬掩模的底部部分去除保形碳层，以暴露硬掩模，在底部蚀刻暴露的硬掩模基板，随后同时去除 保形碳层，光致抗蚀剂等碳质成分。 因此产生了用于进一步模式转移的尺寸减小特征的硬掩模。

公开(公告)号：US09318383B2

公开(公告)日：2016-04-19

申请号：US14923957

申请日：2015-10-27

Applicant: Applied Materials, Inc.

Inventor： Mehul B. Naik ,  Abhijit Basu Mallick ,  Kiran V. Thadani ,  Zhenjiang Cui

IPC: H01L21/44 ,  H01L21/768

CPC classification number: H01L21/76885 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76867 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53261 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention generally relate to methods for forming a metal structure and passivation layers. In one embodiment, metal columns are formed on a substrate. The metal columns are doped with manganese, aluminum, zirconium, or hafnium. A dielectric material is deposited over and between the metal columns and then cured to form a passivation layer on vertical surfaces of the metal columns.

公开(公告)号：US09184093B2

公开(公告)日：2015-11-10

申请号：US14180098

申请日：2014-02-13

Applicant: Applied Materials, Inc.

Inventor： Mehul B. Naik ,  Abhijit Basu Mallick ,  Kiran V. Thadani ,  Zhenjiang Cui

IPC: H01L21/44 ,  H01L21/768 ,  H01L23/532

CPC classification number: H01L21/76885 ,  H01L21/76834 ,  H01L21/76852 ,  H01L21/76867 ,  H01L23/53233 ,  H01L23/53238 ,  H01L23/53261 ,  H01L23/53266 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Embodiments of the present invention generally relate to methods for forming a metal structure and passivation layers. In one embodiment, metal columns are formed on a substrate. The metal columns are doped with manganese, aluminum, zirconium, or hafnium. A dielectric material is deposited over and between the metal columns and then cured to form a passivation layer on vertical surfaces of the metal columns.

Abstract translation: 本发明的实施例一般涉及用于形成金属结构和钝化层的方法。 在一个实施例中，在衬底上形成金属柱。 金属柱掺杂有锰，铝，锆或铪。 介电材料沉积在金属柱之上和之间，然后固化以在金属柱的垂直表面上形成钝化层。

公开(公告)号：US11923244B2

公开(公告)日：2024-03-05

申请号：US17193994

申请日：2021-03-05

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Hao Jiang ,  Shi You ,  Mehul B. Naik

IPC: H01L21/768

CPC classification number: H01L21/76843 ,  H01L21/76879

Abstract: Embodiments of the present disclosure generally relate to subtractive metals, subtractive metal semiconductor structures, subtractive metal interconnects, and to processes for forming such semiconductor structures and interconnects. In an embodiment, a process for fabricating a semiconductor structure is provided. The process includes performing a degas operation on the semiconductor structure and depositing a liner layer on the semiconductor structure. The process further includes performing a sputter operation on the semiconductor structure, and depositing, by physical vapor deposition, a metal layer on the liner layer, wherein the liner layer comprises Ti, Ta, TaN, or combinations thereof, and a resistivity of the metal layer is about 30 μΩ·cm or less.

公开(公告)号：US11101174B2

公开(公告)日：2021-08-24

申请号：US16653601

申请日：2019-10-15

Applicant: Applied Materials, Inc.

Inventor： Hao Jiang ,  Nikolaos Bekiaris ,  Erica Chen ,  Mehul B. Naik

IPC: H01L21/00 ,  H01L21/768 ,  H01L21/762 ,  H01L21/285 ,  H01L21/02 ,  H01L21/30 ,  H01L21/324 ,  H01L21/3213

Abstract: Methods for forming an interconnections structure on a substrate in a cluster processing system and thermal processing such interconnections structure are provided. In one embodiment, a method for a device structure for semiconductor devices includes forming a barrier layer in an opening formed in a material layer disposed on a substrate, forming an interface layer on the barrier layer, forming a gap filling layer on the interface layer, and performing an annealing process on the substrate, wherein the annealing process is performed at a pressure range greater than 5 bar.

公开(公告)号：US10546742B2

公开(公告)日：2020-01-28

申请号：US16237407

申请日：2018-12-31

Applicant: Applied Materials, Inc.

Inventor： He Ren ,  Mehul B. Naik ,  Yong Cao ,  Yana Cheng ,  Weifeng Ye

IPC: H01L21/02 ,  H01L21/768

Abstract: The present disclosure provides an interconnect formed on a substrate and methods for forming the interconnect on the substrate. In one embodiment, the method for forming an interconnect on a substrate includes depositing a barrier layer on the substrate, depositing a transition layer on the barrier layer, and depositing an etch-stop layer on the transition layer, wherein the transition layer shares a common element with the barrier layer, and wherein the transition layer shares a common element with the etch-stop layer.