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    Methods for forming a metal silicide interconnection nanowire structure
    2.
    发明授权
    Methods for forming a metal silicide interconnection nanowire structure 有权

    公开(公告)号：US10930472B2

    公开(公告)日：2021-02-23

    申请号：US16250763

    申请日：2019-01-17

    申请人： Applied Materials, Inc.

    发明人： Bencherki Mebarki ,  Annamalai Lakshmanan ,  Kaushal K. Singh ,  Andrew Cockburn ,  Ludovic Godet ,  Paul F. Ma ,  Mehul B. Naik

    IPC分类号： H01J37/32 ,  C23C16/42 ,  C23C16/56 ,  H01L21/285 ,  H01L21/768 ,  H01L21/3205 ,  H01L21/268

    摘要： Methods and apparatus for forming a metal silicide as nanowires for back-end interconnection structures for semiconductor applications are provided. In one embodiment, the method includes forming a metal silicide layer on a substrate by a chemical vapor deposition process or a physical vapor deposition process, thermal treating the metal silicide layer in a processing chamber, applying a microwave power in the processing chamber while thermal treating the metal silicide layer; and maintaining a substrate temperature less than 400 degrees Celsius while thermal treating the metal silicide layer. In another embodiment, a method includes supplying a deposition gas mixture including at least a metal containing precursor and a reacting gas on a surface of a substrate, forming a plasma in the presence of the deposition gas mixture by exposure to microwave power, exposing the plasma to light radiation, and forming a metal silicide layer on the substrate from the deposition gas.

    Method for critical dimension reduction using conformal carbon films
    5.
    发明授权
    Method for critical dimension reduction using conformal carbon films 有权
    使用保形碳膜进行临界尺寸降低的方法

    公开(公告)号：US09337051B2

    公开(公告)日：2016-05-10

    申请号：US14799374

    申请日：2015-07-14

    申请人： Applied Materials, Inc.

    发明人： Bencherki Mebarki ,  Bok Hoen Kim ,  Deenesh Padhi ,  Li Yan Miao ,  Pramit Manna ,  Christopher Dennis Bencher ,  Mehul B. Naik ,  Huixiong Dai ,  Christopher S. Ngai ,  Daniel Lee Diehl

    IPC分类号： H01L21/00 ,  H01L21/308 ,  H01L21/311 ,  H01L21/02 ,  H01L21/027

    CPC分类号： H01L21/3088 ,  H01L21/02115 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/0276 ,  H01L21/0337 ,  H01L21/3081 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/31144

    摘要： Embodiments of the disclosure generally provide a method of forming a reduced dimension pattern in a hardmask that is optically matched to an overlying photoresist layer. The method generally comprises of application of a dimension shrinking conformal carbon layer over the field region, sidewalls, and bottom portion of the patterned photoresist and the underlying hardmask at temperatures below the decomposition temperature of the photoresist. The methods and embodiments herein further involve removal of the conformal carbon layer from the bottom portion of the patterned photoresist and the hardmask by an etch process to expose the hardmask, etching the exposed hardmask substrate at the bottom portion, followed by the simultaneous removal of the conformal carbon layer, the photoresist, and other carbonaceous components. A hardmask with reduced dimension features for further pattern transfer is thus yielded.

    摘要翻译： 本公开的实施例通常提供在与上覆光致抗蚀剂层光学匹配的硬掩模中形成减小尺寸图案的方法。 该方法通常包括在低于光致抗蚀剂的分解温度的温度下，在图案化的光致抗蚀剂和下面的硬掩模的场区域，侧壁和底部上施加尺寸收缩的保形碳层。 本文的方法和实施例还涉及通过蚀刻工艺从图案化的光致抗蚀剂和硬掩模的底部部分去除保形碳层，以暴露硬掩模，在底部蚀刻暴露的硬掩模基板，随后同时去除 保形碳层，光致抗蚀剂等碳质成分。 因此产生了用于进一步模式转移的尺寸减小特征的硬掩模。

    Subtractive metals and subtractive metal semiconductor structures
    8.
    发明授权
    Subtractive metals and subtractive metal semiconductor structures 有权

    公开(公告)号：US11923244B2

    公开(公告)日：2024-03-05

    申请号：US17193994

    申请日：2021-03-05

    申请人： Applied Materials, Inc.

    发明人： He Ren ,  Hao Jiang ,  Shi You ,  Mehul B. Naik

    IPC分类号： H01L21/768

    CPC分类号： H01L21/76843 ,  H01L21/76879

    摘要： Embodiments of the present disclosure generally relate to subtractive metals, subtractive metal semiconductor structures, subtractive metal interconnects, and to processes for forming such semiconductor structures and interconnects. In an embodiment, a process for fabricating a semiconductor structure is provided. The process includes performing a degas operation on the semiconductor structure and depositing a liner layer on the semiconductor structure. The process further includes performing a sputter operation on the semiconductor structure, and depositing, by physical vapor deposition, a metal layer on the liner layer, wherein the liner layer comprises Ti, Ta, TaN, or combinations thereof, and a resistivity of the metal layer is about 30 μΩ·cm or less.