Invention Grant
- Patent Title: Gap fill deposition process
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Application No.: US16653601Application Date: 2019-10-15
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Publication No.: US11101174B2Publication Date: 2021-08-24
- Inventor: Hao Jiang , Nikolaos Bekiaris , Erica Chen , Mehul B. Naik
- Applicant: Applied Materials, Inc.
- Applicant Address: US CA Santa Clara
- Assignee: Applied Materials, Inc.
- Current Assignee: Applied Materials, Inc.
- Current Assignee Address: US CA Santa Clara
- Agency: Patterson + Sheridan, LLP
- Main IPC: H01L21/00
- IPC: H01L21/00 ; H01L21/768 ; H01L21/762 ; H01L21/285 ; H01L21/02 ; H01L21/30 ; H01L21/324 ; H01L21/3213

Abstract:
Methods for forming an interconnections structure on a substrate in a cluster processing system and thermal processing such interconnections structure are provided. In one embodiment, a method for a device structure for semiconductor devices includes forming a barrier layer in an opening formed in a material layer disposed on a substrate, forming an interface layer on the barrier layer, forming a gap filling layer on the interface layer, and performing an annealing process on the substrate, wherein the annealing process is performed at a pressure range greater than 5 bar.
Public/Granted literature
- US20210111067A1 GAP FILL DEPOSITION PROCESS Public/Granted day:2021-04-15
Information query
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