公开(公告)号：US20050051845A1

公开(公告)日：2005-03-10

申请号：US10910576

申请日：2004-08-04

申请人： Yoshikazu Nakagawa ,  Naoki Izumi

发明人： Yoshikazu Nakagawa ,  Naoki Izumi

IPC分类号： H01L21/28 ,  H01L21/00 ,  H01L21/8238 ,  H01L27/092 ,  H01L29/417 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78

CPC分类号： H01L21/823835 ,  H01L21/823842

摘要： A gate electrode in an NMOS region is one of intrinsic silicon and a material having a work function equivalent to that of intrinsic silicon, and a material having a work function smaller than that of intrinsic silicon. A gate electrode in a PMOS region is one of intrinsic silicon and a material having a work function equivalent to that of intrinsic silicon, and a material having a work function larger than that of intrinsic silicon. Further, a source/drain region in the NMOS region includes a silicide layer of a material having a work function smaller than that of intrinsic silicon, and a source/drain region in the PMOS region includes a silicide layer of a material having a work function larger than that of intrinsic silicon.

摘要翻译： NMOS区域中的栅电极是本征硅和具有与本征硅相同功函数的材料之一，以及功函数小于本征硅的功函数的材料。 PMOS区域中的栅电极是本征硅和具有与本征硅的功函数相当的功函数的材料之一，以及功函数大于本征硅的功函数的材料。 此外，NMOS区域中的源极/漏极区域包括具有比本征硅的功函数小的功函数的硅化物层，并且PMOS区中的源极/漏极区包括具有功函数的材料的硅化物层 大于本征硅。

公开(公告)号：US06404040B1

公开(公告)日：2002-06-11

申请号：US09497157

申请日：2000-02-03

申请人： Junichi Hikita ,  Yoshikazu Nakagawa ,  Nobuhisa Kumamoto

发明人： Junichi Hikita ,  Yoshikazu Nakagawa ,  Nobuhisa Kumamoto

IPC分类号： H01L2358

CPC分类号： H01L25/0657 ,  H01L23/50 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05572 ,  H01L2224/11 ,  H01L2224/1147 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16145 ,  H01L2225/06513 ,  H01L2225/06551 ,  H01L2225/06582 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/10329 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2224/05644 ,  H01L2224/05669 ,  H01L2224/05099

摘要： A semiconductor device having a metal layer at the peripheral area surrounding an element forming area formed on a semiconductor substrate. This metal layer may be connected to the grounding potential or the power potential. The peripheral area is a scribing line area for example. The metal layer may be formed simultaneously with the formation of a bump within the element forming area.

摘要翻译： 一种在围绕形成在半导体衬底上的元件形成区域的周边区域具有金属层的半导体器件。 该金属层可以连接到接地电位或电源电位。 外围区域是例如划线区域。 金属层可以与在元件形成区域内形成凸块同时形成。

公开(公告)号：US5343056A

公开(公告)日：1994-08-30

申请号：US931042

申请日：1992-08-17

申请人： Yoshikazu Nakagawa

发明人： Yoshikazu Nakagawa

IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L29/08 ,  H01L29/36 ,  H01L29/778 ,  H01L29/205 ,  H01L29/161 ,  H01L29/80

CPC分类号： H01L29/0891 ,  H01L29/365 ,  H01L29/7787

摘要： A compound semiconductor device includes an undoped semiconductor layer; a doped semiconductor layer formed on the undoped semiconductor layer and having smaller electron affinity than the undoped semiconductor layer, impurities being doped in the doped semiconductor layer; a gate electrode formed on the doped semiconductor layer; and a source electrode and a drain electrode respectively formed at both sides of the gate electrode, wherein an impurity concentration of the doped semiconductor layer is selected such that a portion of the doped semiconductor layer located immediately below the gate electrode is not completely depleted in a state in which a gate voltage is not applied to the gate electrode, and is completely depleted in a state in which a negative voltage for minimizing a noise figure is applied to the gate electrode.

摘要翻译： 化合物半导体器件包括未掺杂的半导体层; 形成在未掺杂的半导体层上并且具有比未掺杂的半导体层更小的电子亲和力的掺杂半导体层，掺杂半导体层中的杂质; 形成在所述掺杂半导体层上的栅电极; 以及分别形成在栅电极的两侧的源电极和漏电极，其中选择掺杂半导体层的杂质浓度，使得位于栅电极正下方的掺杂半导体层的一部分未完全耗尽 栅极电压不施加到栅电极的状态，并且在用于使噪声系数最小化的负电压施加到栅电极的状态下完全耗尽。

公开(公告)号：US5321278A

公开(公告)日：1994-06-14

申请号：US894780

申请日：1992-06-05

申请人： Yoshikazu Nakagawa

发明人： Yoshikazu Nakagawa

IPC分类号： H01L29/812 ,  H01L21/338 ,  H01L29/778 ,  H01L29/06 ,  H01L31/072 ,  H01L31/109

CPC分类号： H01L29/7787

摘要： A field-effect transistor (FET) in which an InGaAs layer formed on a GaAs substrate is formed in such a manner that the In composition ratio on the gate electrode side on the substrate surface is made small and the In composition ratio on the GaAs substrate side is made large. Thereby, the FET does not cause a decline in the mutual conductance in the FET and a decline in the noise figure (NF) even if negative voltage is applied to a gate electrode.

摘要翻译： 形成在GaAs衬底上形成的InGaAs层的场效应晶体管（FET）以使得衬底表面上的栅电极侧的In组成比变小并且GaAs衬底上的In组成比 一边做得很大。 因此，即使负电压施加到栅电极，FET也不会导致FET中的互导性的下降和噪声系数（NF）的下降。

公开(公告)号：US20090078995A1

公开(公告)日：2009-03-26

申请号：US12232582

申请日：2008-09-19

申请人： Yoshikazu Nakagawa ,  Naoki Izumi ,  Masaki Nagata

发明人： Yoshikazu Nakagawa ,  Naoki Izumi ,  Masaki Nagata

IPC分类号： H01L21/336 ,  H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4925 ,  H01L29/512 ,  H01L29/66734

摘要： A semiconductor device includes a first conductivity type layer of a first conductivity type, a body layer of a second conductivity type formed on the first conductivity type layer, a gate trench passing through the body layer so that the deepest portion thereof reaches the first conductivity type layer, a source region of the first conductivity type formed around the gate trench on the surface layer portion of the body layer, a gate insulating film formed on the bottom surface and the side surface of the gate trench, and a gate electrode embedded in the gate trench through the gate insulating film, and the bottom surface of the gate electrode and the upper surface of the first conductivity type layer are flush with each other.

摘要翻译： 半导体器件包括第一导电类型的第一导电类型，形成在第一导电类型层上的第二导电类型的主体层，穿过主体层的栅极沟槽，使得其最深部分达到第一导电类型 层，形成在主体层的表层部分上的栅极沟槽周围的第一导电类型的源极区，形成在栅极沟槽的底表面和侧表面上的栅极绝缘膜，以及嵌入在栅极电极中的栅电极 通过栅极绝缘膜的栅极沟槽，栅电极的底表面和第一导电类型层的上表面彼此齐平。

公开(公告)号：US06965166B2

公开(公告)日：2005-11-15

申请号：US10373692

申请日：2003-02-27

申请人： Junichi Hikita ,  Yoshikazu Nakagawa ,  Koji Yamamoto

发明人： Junichi Hikita ,  Yoshikazu Nakagawa ,  Koji Yamamoto

IPC分类号： H01L21/56 ,  H01L21/60 ,  H01L21/98 ,  H01L23/31 ,  H01L23/36 ,  H01L23/48 ,  H01L23/485 ,  H01L23/498 ,  H01L25/065 ,  H01L29/06

CPC分类号： H01L24/13 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/36 ,  H01L23/49816 ,  H01L24/11 ,  H01L24/73 ,  H01L24/81 ,  H01L25/0657 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/0401 ,  H01L2224/05124 ,  H01L2224/05166 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0603 ,  H01L2224/10135 ,  H01L2224/10165 ,  H01L2224/11334 ,  H01L2224/1147 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/1403 ,  H01L2224/14051 ,  H01L2224/141 ,  H01L2224/16145 ,  H01L2224/17517 ,  H01L2224/81136 ,  H01L2224/81139 ,  H01L2224/81141 ,  H01L2224/81801 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/0001 ,  H01L2924/01013 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/3511 ,  H01L2924/00014 ,  H01L2924/01074 ,  H01L2924/013

摘要： A semiconductor device including a first semiconductor chip, a second semiconductor chip bonded to the first semiconductor chip in a stacked relation, and a registration structure which causes the first and second semiconductor chips to be positioned with respect to each other by depression-projection engagement therebetween. The registration structure includes, for example, a registration recess provided on a surface of the first semiconductor chip, and a registration projection provided on a surface of the second semiconductor chip for engagement with the registration recess. The registration projection may be a spherical member provided on the surface of the second semiconductor chip.

摘要翻译： 一种半导体器件，包括第一半导体芯片，以堆叠关系结合到第一半导体芯片的第二半导体芯片，以及配准结构，其使得第一半导体芯片和第二半导体芯片通过其间的凹凸突起相互相对于彼此定位 。 配准结构包括例如设置在第一半导体芯片的表面上的配准凹槽以及设置在第二半导体芯片的表面上用于与配准凹槽接合的配准突起。 配准突起可以是设置在第二半导体芯片的表面上的球形部件。

公开(公告)号：US5366849A

公开(公告)日：1994-11-22

申请号：US978263

申请日：1992-11-18

申请人： Yoshikazu Nakagawa ,  Masayuki Sonobe

发明人： Yoshikazu Nakagawa ,  Masayuki Sonobe

IPC分类号： H01L21/28 ,  G03F7/20 ,  H01L21/027 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/338 ,  H01L29/812 ,  G03C5/58

CPC分类号： G03F7/201 ,  Y10S438/947

摘要： The fine pattern processing method comprises an exposure step for forming a resist pattern having a predetermined opening on a substrate, a vapor deposition step for forming a vapor deposited film on a portion of the substrate which is exposed at the opening by performing an inclined vapor deposition over the resist pattern, and an etching step for performing the etching treatment with use of the vapor deposited film as a mask. In the exposure step, the exposure time of the photoresist is continuously varied within the wafer plane in relation to the continuous changes in the vapor deposition angles within the wafer plane during the inclined vapor deposition, so that the taper angle of the resist pattern is changed. In other words, the exposure time is shortened at the region where the vapor deposition angle is small so as to increase the taper angle of the resist pattern, whereas the exposure time is prolonged at the region where the vapor deposition angle is large in order that the taper angle is decreased.

摘要翻译： 精细图案处理方法包括：在基板上形成具有预定开口的抗蚀剂图案的曝光步骤，在基板的一部分上形成气相沉积膜的气相沉积步骤，其通过进行倾斜气相沉积 以及利用蒸镀膜作为掩模进行蚀刻处理的蚀刻工序。 在曝光步骤中，相对于在倾斜气相沉积期间晶片平面内的气相沉积角度的连续变化，光致抗蚀剂的曝光时间在晶片平面内连续变化，使得抗蚀剂图案的锥角变化 。 换句话说，在气相沉积角度较小的区域，曝光时间缩短，从而增加抗蚀剂图案的锥角，而曝光时间在蒸镀角度大的区域延长，以便于 锥角减小。

公开(公告)号：US5296728A

公开(公告)日：1994-03-22

申请号：US23151

申请日：1993-02-24

申请人： Yoshikazu Nakagawa

发明人： Yoshikazu Nakagawa

IPC分类号： H01L29/812 ,  H01L21/285 ,  H01L21/335 ,  H01L21/338 ,  H01L29/47 ,  H01L29/778 ,  H01L29/80 ,  H01L31/112

CPC分类号： H01L29/66462 ,  H01L21/28587 ,  H01L29/475 ,  H01L29/7787 ,  Y10S148/056 ,  Y10S438/951

摘要： A compound semiconductor device includes a first semiconductor layer, a second semiconductor layer providing source and drain regions, and a composite layer consisting of a bottom SiN layer, and SiON layer and a top SiN layer on the second semiconductor layer. A gate electrode has a perpendicular portion extending through an opening in the composite layer and an enlarged region above the top SiN layer to support the electrode at a position closer to the source region than the drain region, and the bottom SiN layer and the SiON layer are recessed so as to be spaced from the gate electrode.

摘要翻译： 化合物半导体器件包括第一半导体层，提供源极和漏极区域的第二半导体层，以及由第二半导体层上的底部SiN层和SiON层和顶部SiN层组成的复合层。 栅电极具有延伸穿过复合层中的开口的垂直部分和顶部SiN层上方的扩大区域，以将电极支撑在比漏极区更靠近源极区域的位置处，并且底部SiN层和SiON层 凹入以与栅电极间隔开。

公开(公告)号：US5110751A

公开(公告)日：1992-05-05

申请号：US658218

申请日：1991-02-20

申请人： Yoshikazu Nakagawa

发明人： Yoshikazu Nakagawa

IPC分类号： H01L29/812 ,  H01L21/285 ,  H01L21/335 ,  H01L21/338 ,  H01L29/47 ,  H01L29/778

CPC分类号： H01L29/66462 ,  H01L21/28587 ,  H01L29/475 ,  H01L29/7787 ,  Y10S148/056 ,  Y10S438/951

摘要： A first semiconductor layer, a second semiconductor layer for source and drain regions, and a bottom SiN layer are successively formed. After the bottom SiN layer is selectively etched to make an opening, a SiON layer and a top SiN layer are formed thereon. A resist pattern having an opening that is closer to the source region than to the drain region is formed on the top SiN layer. The top SiN layer and SiON layer are etched with the resist pattern used as a mask, to expose the second semiconductor layer. The SiON layer is side-etched with hydrofluoric acid until exposing the gate-side portion of the source-side bottom SiN layer. Then, the second semiconductor layer is etched to expose the first semiconductor layer and to form the source and drain regions, where the gate-side edge of the source region is determined by that of the source-side bottom SiN layer and the gate-side edge of the drain region is determined by that of the drain-side SiON layer. Finally, a gate metal is vapor-deposited vertically on the first semiconductor layer with the opening of the top SiN layer used as a mask.

公开(公告)号：US08384152B2

公开(公告)日：2013-02-26

申请号：US12232582

申请日：2008-09-19

申请人： Yoshikazu Nakagawa ,  Naoki Izumi ,  Masaki Nagata

发明人： Yoshikazu Nakagawa ,  Naoki Izumi ,  Masaki Nagata

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4925 ,  H01L29/512 ,  H01L29/66734

摘要： A semiconductor device includes a first conductivity type layer of a first conductivity type, a body layer of a second conductivity type formed on the first conductivity type layer, a gate trench passing through the body layer so that the deepest portion thereof reaches the first conductivity type layer, a source region of the first conductivity type formed around the gate trench on the surface layer portion of the body layer, a gate insulating film formed on the bottom surface and the side surface of the gate trench, and a gate electrode embedded in the gate trench through the gate insulating film, and the bottom surface of the gate electrode and the upper surface of the first conductivity type layer are flush with each other.

摘要翻译： 半导体器件包括第一导电类型的第一导电类型，形成在第一导电类型层上的第二导电类型的主体层，穿过主体层的栅极沟槽，使得其最深部分达到第一导电类型 层，形成在主体层的表层部分上的栅极沟槽周围的第一导电类型的源极区，形成在栅极沟槽的底表面和侧表面上的栅极绝缘膜，以及嵌入在栅极电极中的栅电极 通过栅极绝缘膜的栅极沟槽，栅电极的底表面和第一导电类型层的上表面彼此齐平。