公开(公告)号：US08384152B2

公开(公告)日：2013-02-26

申请号：US12232582

申请日：2008-09-19

申请人： Yoshikazu Nakagawa ,  Naoki Izumi ,  Masaki Nagata

发明人： Yoshikazu Nakagawa ,  Naoki Izumi ,  Masaki Nagata

IPC分类号： H01L29/66

CPC分类号： H01L29/7813 ,  H01L29/0623 ,  H01L29/0878 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/4925 ,  H01L29/512 ,  H01L29/66734

摘要： A semiconductor device includes a first conductivity type layer of a first conductivity type, a body layer of a second conductivity type formed on the first conductivity type layer, a gate trench passing through the body layer so that the deepest portion thereof reaches the first conductivity type layer, a source region of the first conductivity type formed around the gate trench on the surface layer portion of the body layer, a gate insulating film formed on the bottom surface and the side surface of the gate trench, and a gate electrode embedded in the gate trench through the gate insulating film, and the bottom surface of the gate electrode and the upper surface of the first conductivity type layer are flush with each other.

摘要翻译： 半导体器件包括第一导电类型的第一导电类型，形成在第一导电类型层上的第二导电类型的主体层，穿过主体层的栅极沟槽，使得其最深部分达到第一导电类型 层，形成在主体层的表层部分上的栅极沟槽周围的第一导电类型的源极区，形成在栅极沟槽的底表面和侧表面上的栅极绝缘膜，以及嵌入在栅极电极中的栅电极 通过栅极绝缘膜的栅极沟槽，栅电极的底表面和第一导电类型层的上表面彼此齐平。

公开(公告)号：US08258604B2

公开(公告)日：2012-09-04

申请号：US12647445

申请日：2009-12-26

申请人： Koji Bando ,  Kazuyuki Misumi ,  Tatsuhiko Akiyama ,  Naoki Izumi ,  Akira Yamazaki

发明人： Koji Bando ,  Kazuyuki Misumi ,  Tatsuhiko Akiyama ,  Naoki Izumi ,  Akira Yamazaki

IPC分类号： H01L23/552

CPC分类号： H01L23/49503 ,  G11C11/16 ,  H01L23/552 ,  H01L24/32 ,  H01L24/33 ,  H01L24/45 ,  H01L24/48 ,  H01L27/228 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/4824 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/4826 ,  H01L2224/73265 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/0102 ,  H01L2924/01023 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/01042 ,  H01L2924/01046 ,  H01L2924/01061 ,  H01L2924/01064 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/0132 ,  H01L2924/0133 ,  H01L2924/014 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/01026 ,  H01L2924/01028 ,  H01L2924/3512 ,  H01L2224/05599 ,  H01L2924/00012

摘要： To provide a technique that can improve the data retention characteristic of an MRAM device by improving the resistance against an external magnetic field in a semiconductor device including the MRAM device.A first magnetic shield material is disposed over a die pad via a first die attach film. Then, a semiconductor chip is mounted over the first magnetic shield material via a second die attach film. Furthermore, a second magnetic shield material is disposed over the semiconductor chip via a third die attach film. That is, the semiconductor chip is disposed so as to be sandwiched by the first magnetic shield material and the second magnetic shield material. At this time, while the planar area of the second magnetic shield material is smaller than that of the first magnetic shield material, the thickness of the second magnetic shield material is thicker than that of the first magnetic shield material.

摘要翻译： 提供一种通过提高包括MRAM器件的半导体器件中的外部磁场的电阻来提高MRAM器件的数据保持特性的技术。 第一磁屏蔽材料经由第一管芯附着膜设置在管芯焊盘上。 然后，半导体芯片通过第二芯片附着膜安装在第一磁屏蔽材料上。 此外，第二磁屏蔽材料通过第三芯片附着膜设置在半导体芯片的上方。 也就是说，半导体芯片被布置成被第一磁屏蔽材料和第二磁屏蔽材料夹在中间。 此时，当第二磁屏蔽材料的平面区域小于第一磁屏蔽材料的平面区域时，第二磁屏蔽材料的厚度比第一磁屏蔽材料的厚度厚。

公开(公告)号：US08247866B2

公开(公告)日：2012-08-21

申请号：US13137099

申请日：2011-07-20

申请人： Naoki Izumi

发明人： Naoki Izumi

IPC分类号： H01L23/62

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0626 ,  H01L29/0696 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： An inventive semiconductor device includes: a semiconductor layer; a drift region of a first conductivity type provided in the semiconductor layer; a body region of a second conductivity type provided on the drift region in the semiconductor layer; a trench extending from a surface of the body region in the semiconductor layer with its bottom located in the drift region; a gate insulation film provided on an interior surface of the trench; a gate electrode provided in the trench with the intervention of the gate insulation film; a source region of the first conductivity type provided in the surface of the body region; a first impurity region of the second conductivity type provided around the bottom of the trench in spaced relation from the body region; and a second impurity region of the second conductivity type provided on a lateral side of the body region in the semiconductor layer, the second impurity region being isolated from the body region and electrically connected to the first impurity region.

摘要翻译： 本发明的半导体器件包括：半导体层; 提供在半导体层中的第一导电类型的漂移区; 设置在半导体层中的漂移区上的第二导电类型的体区; 从半导体层中的本体区域的表面延伸的沟槽，其底部位于漂移区域中; 设置在沟槽的内表面上的栅极绝缘膜; 栅极电极，设置在沟槽中，介入栅极绝缘膜; 设置在所述身体区域的表面中的所述第一导电类型的源极区域; 第二导电类型的第一杂质区域设置在与体区间隔开的沟槽的底部周围; 以及第二导电类型的第二杂质区域，设置在半导体层中的体区域的侧面上，第二杂质区域与体区隔离并电连接到第一杂质区域。

公开(公告)号：US20120146137A1

公开(公告)日：2012-06-14

申请号：US13371501

申请日：2012-02-13

申请人： Naoki IZUMI

发明人： Naoki IZUMI

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/7813 ,  H01L29/41775 ,  H01L29/4236 ,  H01L29/42368 ,  H01L29/66734

摘要： A semiconductor device according to the present invention includes a semiconductor layer. A first conductivity type region is formed on a base layer portion of the semiconductor layer. A body region of a second conductivity type is formed on the semiconductor layer to be in contact with the first conductivity type region. A trench in which a gate electrode is embedded through a gate insulating film is formed on the semiconductor layer. The trench penetrates through the body region, so that a deepest portion thereof reaches the first conductivity type region. A source region of the first conductivity type is formed on a surface layer portion of the semiconductor layer around the trench. The gate insulating film includes a thick-film portion having a relatively large thickness on a bottom surface of the trench.

摘要翻译： 根据本发明的半导体器件包括半导体层。 第一导电类型区域形成在半导体层的基底层部分上。 在半导体层上形成与第一导电类型区域接触的第二导电类型的体区。 在半导体层上形成有通过栅极绝缘膜嵌入栅电极的沟槽。 沟槽穿过身体区域，使得其最深部分到达第一导电类型区域。 第一导电类型的源区形成在沟槽周围的半导体层的表层部分上。 栅极绝缘膜包括在沟槽的底表面上具有相对较大厚度的厚膜部分。

公开(公告)号：US20110278664A1

公开(公告)日：2011-11-17

申请号：US13137099

申请日：2011-07-20

申请人： Naoki Izumi

发明人： Naoki Izumi

IPC分类号： H01L29/78

CPC分类号： H01L29/7813 ,  H01L29/0619 ,  H01L29/0623 ,  H01L29/0626 ,  H01L29/0696 ,  H01L29/66734 ,  H01L29/7808 ,  H01L29/7811 ,  H01L2924/0002 ,  H01L2924/00

摘要： An inventive semiconductor device includes: a semiconductor layer; a drift region of a first conductivity type provided in the semiconductor layer; a body region of a second conductivity type provided on the drift region in the semiconductor layer; a trench extending from a surface of the body region in the semiconductor layer with its bottom located in the drift region; a gate insulation film provided on an interior surface of the trench; a gate electrode provided in the trench with the intervention of the gate insulation film; a source region of the first conductivity type provided in the surface of the body region; a first impurity region of the second conductivity type provided around the bottom of the trench in spaced relation from the body region; and a second impurity region of the second conductivity type provided on a lateral side of the body region in the semiconductor layer, the second impurity region being isolated from the body region and electrically connected to the first impurity region.

摘要翻译： 本发明的半导体器件包括：半导体层; 提供在半导体层中的第一导电类型的漂移区; 设置在半导体层中的漂移区上的第二导电类型的体区; 从半导体层中的本体区域的表面延伸的沟槽，其底部位于漂移区域中; 设置在沟槽的内表面上的栅极绝缘膜; 栅极电极，设置在沟槽中，介入栅极绝缘膜; 设置在所述身体区域的表面中的所述第一导电类型的源极区域; 第二导电类型的第一杂质区域设置在与体区间隔开的沟槽的底部周围; 以及第二导电类型的第二杂质区域，设置在半导体层中的体区域的侧面上，第二杂质区域与体区隔离并电连接到第一杂质区域。

公开(公告)号：US20100261334A1

公开(公告)日：2010-10-14

申请号：US12821703

申请日：2010-06-23

申请人： Hiroyuki CHIBAHARA ,  Atsushi Ishii ,  Naoki Izumi ,  Masahiro Matsumoto

发明人： Hiroyuki CHIBAHARA ,  Atsushi Ishii ,  Naoki Izumi ,  Masahiro Matsumoto

IPC分类号： H01L21/304

CPC分类号： H01L23/02 ,  H01L23/522 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.

摘要翻译： 提供了难以发生由层间电介质膜的破裂引起的密封环破坏的半导体装置，以及半导体装置的制造方法。 第一层压板包括具有第一机械强度的第一层间绝缘膜。 第二层压体包括具有高于第一机械强度的机械强度的第二层间介电膜。 第一区域包括设置在第一层压体内的第一金属层和通孔。 第二区域包括设置在第二层压体内的第二金属层和通孔。 当在平面图中看到时，第二区域与第一区域的至少一部分重叠，不通过通孔与第一区域耦合，并且在其与第一区域之间夹住第二层间电介质膜。

公开(公告)号：US20090294912A1

公开(公告)日：2009-12-03

申请号：US12426588

申请日：2009-04-20

申请人： Hiroyuki Chibahara ,  Atsushi Ishii ,  Naoki Izumi ,  Masahiro Matsumoto

发明人： Hiroyuki Chibahara ,  Atsushi Ishii ,  Naoki Izumi ,  Masahiro Matsumoto

IPC分类号： H01L23/02 ,  H01L21/304

CPC分类号： H01L23/02 ,  H01L23/522 ,  H01L23/585 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device wherein destruction of a sealing ring caused by cracking of an interlayer dielectric film is difficult to occur, as well as a method for manufacturing the semiconductor device, are provided. A first laminate comprises first interlayer dielectric films having a first mechanical strength. A second laminate comprises second interlayer dielectric films having a mechanical strength higher than the first mechanical strength. A first region includes first metallic layers and vias provided within the first laminate. A second region includes second metallic layers and vias provided within the second laminate. When seen in plan, the second region overlaps at least a part of the first region, is not coupled with the first region by vias, and sandwiches the second interlayer dielectric film between it and the first region.

摘要翻译： 提供了难以发生由层间电介质膜的破裂引起的密封环破坏的半导体装置，以及半导体装置的制造方法。 第一层压板包括具有第一机械强度的第一层间绝缘膜。 第二层压体包括具有高于第一机械强度的机械强度的第二层间介电膜。 第一区域包括设置在第一层压体内的第一金属层和通孔。 第二区域包括设置在第二层压体内的第二金属层和通孔。 当在平面图中看到时，第二区域与第一区域的至少一部分重叠，不通过通孔与第一区域耦合，并且在其与第一区域之间夹住第二层间电介质膜。

公开(公告)号：US07598154B2

公开(公告)日：2009-10-06

申请号：US11638500

申请日：2006-12-14

申请人： Naoki Izumi

发明人： Naoki Izumi

IPC分类号： H01L21/44

CPC分类号： H01L21/78 ,  B28D5/022 ,  H01L24/97 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00

摘要： Size of a chipping is made small, suppressing blinding of a blade, when performing dicing of a wafer.When cutting a wafer, cutting is performed so that the portion of a V character-shaped shoulder may enter below the front surface of a wafer (depth Z2 from a substrate front surface) using the metal-bond blade which includes the abrasive particle whose fineness number is more than #3000, and whose point is V character form. By processing it in this way, cutting resistance goes up and blinding of a blade can be prevented. Hereby, the size of a chipping can be suppressed small, preventing blinding of a blade.

摘要翻译： 当进行晶片的切割时，切屑的尺寸变小，抑制叶片的盲目。 当切割晶片时，使用包括磨粒的金属粘合刀片，使V字形肩部的一部分进入晶片的前表面（从基片前表面的深度Z2） 数字超过＃3000，其点为V字符形式。 通过以这种方式进行处理，切割阻力增加，并且可以防止叶片的眩目。 因此，可以抑制切屑的尺寸小，防止叶片的致盲。

公开(公告)号：US20090096018A1

公开(公告)日：2009-04-16

申请号：US12238556

申请日：2008-09-26

申请人： Naoki IZUMI

发明人： Naoki IZUMI

IPC分类号： H01L29/78

CPC分类号： H01L27/088 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/7813

摘要： A semiconductor device according to the present invention includes: a body region of a first conductive type; trenches formed by digging in from a top surface of the body region; gate electrodes embedded in the trenches; source regions of a second conductive type formed at sides of the trenches in a top layer portion of the body region; and body contact regions of the first conductive type, penetrating through the source regions in a thickness direction and contacting the body region. The body contact regions are formed in a zigzag alignment in a plan view. With respect to a column formed by the body contact regions aligned in a predetermined column direction, the trenches are disposed at both sides in a row direction orthogonal to the column direction in a plan view, extend in the column direction, and form meandering lines each connecting a plurality of curved portions so that a predetermined gap in the row direction is formed respectively between adjacent trenches extending in the column direction and between the trenches and the body contact regions.

摘要翻译： 根据本发明的半导体器件包括：第一导电类型的体区; 通过从身体区域的顶表面挖入而形成的沟槽; 嵌入沟槽中的栅电极; 源区域，形成在所述体区域的顶层部分中的所述沟槽的侧面处的第二导电类型; 以及第一导电类型的身体接触区域，其在厚度方向上穿过源区域并接触身体区域。 身体接触区域在平面图中以Z字形排列形成。 对于由预定列方向排列的身体接触区域形成的列，在平面图中沿着与列方向正交的行方向的两侧配置沟槽，在列方向上延伸，并且形成曲折线 连接多个弯曲部分，使得在列方向上延伸的相邻沟槽之间以及沟槽与身体接触区域之间分别形成在行方向上的预定间隙。

公开(公告)号：US20090085113A1

公开(公告)日：2009-04-02

申请号：US12285014

申请日：2008-09-26

申请人： Naoki Izumi ,  Tomoyasu Sada

发明人： Naoki Izumi ,  Tomoyasu Sada

IPC分类号： H01L29/78

CPC分类号： H01L29/7835 ,  H01L29/0623 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/42368

摘要： A semiconductor device according to the present invention includes: a semiconductor layer of a first conductivity type; an annular deep trench penetrating the semiconductor layer in the depth direction to surround an element forming region; a drain region of a second conductivity type formed in a surface layer portion of the semiconductor layer in the element forming region; a drift region of the second conductivity type formed in the surface layer portion of the semiconductor layer to come into contact with the drain region in the element forming region; a body region of the first conductivity type formed in the surface layer portion of the semiconductor layer at an interval from the drift region in the element forming region; a source region of the second conductivity type formed in a surface layer portion of the body region; and a first high-concentration buried region, formed in the semiconductor layer between a portion opposed to the source region in the depth direction and the deep trench, having a higher impurity concentration than that of the semiconductor layer.

摘要翻译： 根据本发明的半导体器件包括：第一导电类型的半导体层; 在深度方向上穿透半导体层的环形深沟槽，以围绕元件形成区域; 形成在元件形成区域中的半导体层的表层部分中的第二导电类型的漏极区域; 所述第二导电类型的漂移区域形成在所述半导体层的所述表面层部分中以与所述元件形成区域中的所述漏极区域接触; 所述第一导电类型的体区域形成在所述半导体层的表面层部分中，与所述元件形成区域中的漂移区域间隔开; 形成在所述身体区域的表层部分中的所述第二导电类型的源极区域; 以及形成在半导体层中的与深度方向的源极区域相对的部分与深沟槽之间的第一高浓度掩埋区域，其杂质浓度高于半导体层的杂质浓度。