公开(公告)号：US08647901B2

公开(公告)日：2014-02-11

申请号：US12137519

申请日：2008-06-11

Applicant: Yih-Der Guo ,  Chih-Ming Lai ,  Jenq-Dar Tsay ,  Po-Chun Liu

Inventor： Yih-Der Guo ,  Chih-Ming Lai ,  Jenq-Dar Tsay ,  Po-Chun Liu

IPC: H01L21/02

CPC classification number: C30B25/02 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/0254 ,  H01L21/0265 ,  H01L21/02664 ,  H01L33/0079

Abstract: There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure. Next, a nitride semiconductor layer is formed over the patterned epitaxy layer connected to the nitride semiconductor layer through the pier structure, wherein the nitride semiconductor layer, the pier structure, and the patterned epitaxy layer together form a space exposing a bottom surface of the nitride semiconductor layer. Thereafter, a weakening process is performed to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between the top surface of the pier structure and the nitride semiconductor layer. Finally, the substrate is separated from the nitride semiconductor layer through the connection point.

Abstract translation: 提供一种形成氮化物半导体层的方法，包括以下步骤：首先提供其上形成有墩结构的图案化外延层的基板。 然后在图案化的外延层上形成保护层，露出墩结构的顶表面。 接下来，在通过墩结构连接到氮化物半导体层的图案化外延层上形成氮化物半导体层，其中氮化物半导体层，墩结构和图案化外延层一起形成暴露氮化物的底表面的空间 半导体层。 此后，执行弱化处理以去除氮化物半导体层的底表面的一部分并削弱墩结构的顶表面和氮化物半导体层之间的连接点。 最后，通过连接点将衬底与氮化物半导体层分离。

公开(公告)号：US08604487B2

公开(公告)日：2013-12-10

申请号：US13329336

申请日：2011-12-19

Applicant: Yen-Hsiang Fang ,  Chu-Li Chao ,  Chih-Wei Hu ,  Yih-Der Guo

Inventor： Yen-Hsiang Fang ,  Chu-Li Chao ,  Chih-Wei Hu ,  Yih-Der Guo

IPC: H01L29/15

CPC classification number: H01L33/0075 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02513 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L33/12

Abstract: A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes a base material, a patterned nitride semiconductor, a protection layer, and a nitride semiconductor layer. The patterned nitride semiconductor layer is located on the base material and includes a plurality of nanorod structures and a plurality of block patterns, and an upper surface of the nanorod structures is substantially coplanar with an upper surface of the block patterns. The protection layer covers a side wall of the nanorod structure sand a side wall of the block patterns. The nitride semiconductor layer is located on the patterned nitride semiconductor layer, and a plurality of nanopores are located between the nitride semiconductor layer and the patterned nitride semiconductor layer.

Abstract translation: 提供一种氮化物半导体衬底及其制造方法。 氮化物半导体衬底包括基底材料，图案化氮化物半导体，保护层和氮化物半导体层。 图案化氮化物半导体层位于基材上并且包括多个纳米棒结构和多个块图案，并且纳米棒结构的上表面与块图案的上表面基本共面。 保护层覆盖纳米棒结构的侧壁，以阻挡块图案的侧壁。 氮化物半导体层位于图案化的氮化物半导体层上，并且多个纳米孔位于氮化物半导体层和图案化氮化物半导体层之间。

公开(公告)号：US20120153338A1

公开(公告)日：2012-06-21

申请号：US12975271

申请日：2010-12-21

Applicant: Yih-Der Guo ,  Chu-Li Chao ,  Yen-Hsiang Fang ,  Ruey-Chyn Yeh ,  Kun-Fong Lin

Inventor： Yih-Der Guo ,  Chu-Li Chao ,  Yen-Hsiang Fang ,  Ruey-Chyn Yeh ,  Kun-Fong Lin

IPC: H01L33/62 ,  H01L29/20 ,  H01L21/20

CPC classification number: H01L33/007 ,  C30B25/183 ,  C30B29/403 ,  H01L33/12

Abstract: A substrate structure is described, including a starting substrate, crystal piers on the starting substrate, and a mask layer. The mask layer covers an upper portion of the sidewall of each crystal pier, is connected between the crystal piers at its bottom, and is separated from the starting substrate by an empty space between the crystal piers. An epitaxial substrate structure is also described, which can be formed by growing an epitaxial layer over the above substrate structure form the crystal piers. The crystal piers may be broken after the epitaxial layer is grown.

Abstract translation: 描述了一种衬底结构，包括起始衬底，起始衬底上的晶体墩和掩模层。 掩模层覆盖每个晶墩的侧壁的上部，连接在其底部的晶体墩之间，并且通过晶体墩之间的空白空间与起始衬底分离。 还描述了外延衬底结构，其可以通过在上述衬底结构上生长外延层形成晶体墩而形成。 在外延层生长之后，晶体墩可能被破坏。

公开(公告)号：US20110003410A1

公开(公告)日：2011-01-06

申请号：US12648308

申请日：2009-12-29

Applicant: Jenq-Dar Tsay ,  Suh-Fang Lin ,  Yu-Hsiang Chang ,  Yih-Der Guo ,  Sheng-Huei Kuo ,  Wei-Hung Kuo ,  Hsun-Chih Liu

Inventor： Jenq-Dar Tsay ,  Suh-Fang Lin ,  Yu-Hsiang Chang ,  Yih-Der Guo ,  Sheng-Huei Kuo ,  Wei-Hung Kuo ,  Hsun-Chih Liu

IPC: H01L33/48 ,  H01L33/60

CPC classification number: H01L33/0079 ,  H01L33/20 ,  H01L33/405 ,  H01L33/44

Abstract: A method of manufacturing a light emitting diode element is provided. A first patterned semi-conductor layer, a patterned light emitting layer, and a second patterned semi-conductor layer are sequentially formed on an epitaxy substrate so as to form a plurality of epitaxy structures, wherein the first patterned semi-conductor layer has a thinner portion in a non-epitaxy area outside the epitaxy structures. A passivation layer covering the epitaxy structures and the thinner portion is formed. The passivation layer covering on the thinner portion is partially removed to form a patterned passivation layer. A patterned reflector is formed directly on each of the epitaxy structures. The epitaxy structures are bonded to a carrier substrate. A lift-off process is performed to separate the epitaxy structures from the epitaxy substrate. An electrode is formed on each of the epitaxy structures far from the patterned reflector.

Abstract translation: 提供一种制造发光二极管元件的方法。 在外延基板上依次形成第一图案化半导体层，图案化发光层和第二图案化半导体层，以形成多个外延结构，其中第一图案化半导体层具有较薄的 部分在外延结构外的非外延区域。 形成覆盖外延结构和较薄部分的钝化层。 覆盖在较薄部分上的钝化层被部分地去除以形成图案化的钝化层。 在每个外延结构上直接形成图案化反射体。 外延结构被结合到载体衬底上。 进行剥离处理以将外延结构与外延基板分离。 在远离图案化反射器的每个外延结构上形成电极。

公开(公告)号：US20100090312A1

公开(公告)日：2010-04-15

申请号：US12584942

申请日：2009-09-14

Applicant: Yih-Der Guo ,  Suh-Fang Lin ,  Wei-Hung Kuo ,  Po-Chun Liu ,  Tung-Wei Chi ,  Chu-Li Chao ,  Jenq-Dar Tsay

Inventor： Yih-Der Guo ,  Suh-Fang Lin ,  Wei-Hung Kuo ,  Po-Chun Liu ,  Tung-Wei Chi ,  Chu-Li Chao ,  Jenq-Dar Tsay

IPC: H01L29/20 ,  H01L21/20 ,  H01L21/04

CPC classification number: C30B25/02 ,  C23C14/0005 ,  C23C14/021 ,  C23C14/0617 ,  C23C16/01 ,  C23C16/0227 ,  C23C16/303 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/02664 ,  H01L33/0079 ,  H01S2304/12

Abstract: A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes an epitaxy substrate, a nitride pillar layer, a nitride semiconductor layer, and a mask layer. The nitride pillar layer includes a plurality of first patterned arranged pillars and a plurality of second patterned arranged pillars. The nitride pillar layer is formed on the epitaxy substrate. A width of a cross-section of each of the second patterned arranged pillars is smaller than a width of a cross-section of each of the first patterned arranged pillars, and a distance among each of the second patterned arranged pillars is longer than a distance among each of the first patterned arranged pillars. Surfaces of the epitaxy substrate, the first patterned arranged pillars, and the second patterned arranged pillars are covered by the mask layer. The nitride semiconductor layer is formed on the nitride pillar layer.

Abstract translation: 提供一种氮化物半导体衬底及其制造方法。 氮化物半导体衬底包括外延衬底，氮化物衬底层，氮化物半导体层和掩模层。 氮化物柱层包括多个第一图案化排列的柱和多个第二图案化排列的柱。 在外延基板上形成氮化物柱层。 每个第二图案化排列的柱的横截面的宽度小于每个第一图案化排列的柱的横截面的宽度，并且每个第二图案化排列的柱之间的距离长于距离 在每个第一图案化排列的柱子中。 外延衬底的表面，第一图案化排列的柱和第二图案化排列的柱被掩模层覆盖。 氮化物半导体层形成在氮化物柱层上。

公开(公告)号：US20100013054A1

公开(公告)日：2010-01-21

申请号：US12551534

申请日：2009-08-31

Applicant: Po-Chun Liu ,  Wen-Yueh Liu ,  Chih-Ming Lai ,  Yih-Der Guo ,  Jenq-Dar Tsay

Inventor： Po-Chun Liu ,  Wen-Yueh Liu ,  Chih-Ming Lai ,  Yih-Der Guo ,  Jenq-Dar Tsay

IPC: H01L29/201

CPC classification number: H01L29/2003 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/02664 ,  H01L21/2007

Abstract: A composite material substrate having patterned structure includes a substrate, a first dielectric layer, a second dielectric layer, and a nitride semiconductor material. Herein, the first dielectric layer is stacked on the substrate, the second dielectric layer is stacked on the first dielectric layer, and the nitride semiconductor material is stacked on the second dielectric layer and is characterized by a plurality of patterns thereon.

Abstract translation: 具有图案化结构的复合材料基板包括基板，第一介电层，第二介质层和氮化物半导体材料。 这里，第一电介质层层叠在基板上，第二介电层层叠在第一电介质层上，氮化物半导体材料层叠在第二电介质层上，其特征在于多个图案。

公开(公告)号：US20090085050A1

公开(公告)日：2009-04-02

申请号：US11948464

申请日：2007-11-30

Applicant: Yih-Der GUO ,  Jenq-Dar TSAY ,  Po-Chun LIU

Inventor： Yih-Der GUO ,  Jenq-Dar TSAY ,  Po-Chun LIU

IPC: H01L21/28 ,  F21V7/00 ,  H05K3/02 ,  F21V21/00 ,  H05K3/00 ,  H01L33/00

CPC classification number: H05K3/4007 ,  H01L33/486 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H05K1/0306 ,  H05K1/053 ,  H05K1/111 ,  H05K1/113 ,  H05K2201/09045 ,  H05K2201/10106 ,  Y10T29/49155 ,  H01L2224/05599

Abstract: An island submount used for carrying at least one light-emitting element having at least one electrical contact. The island submount includes a substrate, at least one island structure having a top surface and an inclined surface, and a conductive layer. The island structure is located on the substrate and corresponds to the electrical contact. The conductive layer is formed on the surface of the island structure and at least covers the top surface, so as to be electrically connected with the electrical contact. The island submount is capable of enhancing the light extraction efficiency of the light-emitting element, and avoids the energy loss due to re-absorption when the light emerging from below the light-emitting element is reflected back to the light-emitting element.

Abstract translation: 用于承载至少一个具有至少一个电触头的发光元件的岛基座。 岛基座包括基板，具有顶表面和倾斜表面的至少一个岛结构和导电层。 岛结构位于基板上并对应于电接触。 导电层形成在岛状结构的表面上，并且至少覆盖顶表面，从而与电触点电连接。 岛基座能够增强发光元件的光提取效率，并且当从发光元件下方出射的光被反射回发光元件时，可以避免由于再吸收而导致的能量损失。

公开(公告)号：US20080054294A1

公开(公告)日：2008-03-06

申请号：US11562422

申请日：2006-11-22

Applicant: Chih-Ming Lai ,  Jenq-Dar Tsay ,  Wen-Yueh Liu ,  Yih-Der Guo

Inventor： Chih-Ming Lai ,  Jenq-Dar Tsay ,  Wen-Yueh Liu ,  Yih-Der Guo

IPC: H01L33/00

CPC classification number: H01L21/02642 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/02463 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647

Abstract: The present invention relates to a method of forming a nitride semiconductor substrate. This method includes steps of providing a substrate and then forming an epitaxy layer on the substrate. A patterned mask layer is formed on the epitaxy layer, wherein the patterned mask layer exposes a portion of the epitaxy layer. Next, an oxidation process is performed to oxidize the exposed epitaxy layer so as to form a plurality of dislocation blocking structures. The patterned mask layer is then removed. Further, a nitride semiconductor layer is formed on the epitaxy layer having the dislocation blocking structures.

Abstract translation: 本发明涉及形成氮化物半导体衬底的方法。 该方法包括提供衬底，然后在衬底上形成外延层的步骤。 在外延层上形成图案化掩模层，其中图案化掩模层暴露外延层的一部分。 接下来，进行氧化处理以氧化暴露的外延层，以形成多个位错阻挡结构。 然后去除图案化的掩模层。 此外，在具有位错阻挡结构的外延层上形成氮化物半导体层。

公开(公告)号：US08188573B2

公开(公告)日：2012-05-29

申请号：US12584942

申请日：2009-09-14

Applicant: Yih-Der Guo ,  Suh-Fang Lin ,  Wei-Hung Kuo

Inventor： Yih-Der Guo ,  Suh-Fang Lin ,  Wei-Hung Kuo

IPC: H01L29/20

CPC classification number: C30B25/02 ,  C23C14/0005 ,  C23C14/021 ,  C23C14/0617 ,  C23C16/01 ,  C23C16/0227 ,  C23C16/303 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/02664 ,  H01L33/0079 ,  H01S2304/12

Abstract: A nitride semiconductor substrate and a method for manufacturing the same are provided. The nitride semiconductor substrate includes an epitaxy substrate, a nitride pillar layer, a nitride semiconductor layer, and a mask layer. The nitride pillar layer includes a plurality of first patterned arranged pillars and a plurality of second patterned arranged pillars. The nitride pillar layer is formed on the epitaxy substrate. A width of a cross-section of each of the second patterned arranged pillars is smaller than a width of a cross-section of each of the first patterned arranged pillars, and a distance among each of the second patterned arranged pillars is longer than a distance among each of the first patterned arranged pillars. Surfaces of the epitaxy substrate, the first patterned arranged pillars, and the second patterned arranged pillars are covered by the mask layer. The nitride semiconductor layer is formed on the nitride pillar layer.

Abstract translation: 提供一种氮化物半导体衬底及其制造方法。 氮化物半导体衬底包括外延衬底，氮化物衬底层，氮化物半导体层和掩模层。 氮化物柱层包括多个第一图案化排列的柱和多个第二图案化排列的柱。 在外延基板上形成氮化物柱层。 每个第二图案化排列的柱的横截面的宽度小于每个第一图案化排列的柱的横截面的宽度，并且每个第二图案化排列的柱之间的距离长于距离 在每个第一图案化排列的柱子中。 外延衬底的表面，第一图案化排列的柱和第二图案化排列的柱被掩模层覆盖。 氮化物半导体层形成在氮化物柱层上。

公开(公告)号：US20120119220A1

公开(公告)日：2012-05-17

申请号：US13355108

申请日：2012-01-20

Applicant: Yih-Der Guo ,  Suh-Fang Lin ,  Wei-Hung Kuo ,  Po-Chun Liu ,  Tung-Wei Chi ,  Chu-Li Chao ,  Jenq-Dar Tsay

Inventor： Yih-Der Guo ,  Suh-Fang Lin ,  Wei-Hung Kuo ,  Po-Chun Liu ,  Tung-Wei Chi ,  Chu-Li Chao ,  Jenq-Dar Tsay

IPC: H01L29/20

CPC classification number: C30B25/02 ,  C23C14/0005 ,  C23C14/021 ,  C23C14/0617 ,  C23C16/01 ,  C23C16/0227 ,  C23C16/303 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/02458 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/0265 ,  H01L21/02664 ,  H01L33/0079 ,  H01S2304/12

Abstract: A nitride semiconductor substrate includes an epitaxy substrate, a patterned nitride semiconductor pillar layer, a nitride semiconductor layer, and a mask layer is provided. The nitride semiconductor pillar layer includes a plurality of first patterned arranged hollow structures and a plurality of second patterned arranged hollow structures formed among the first patterned arranged hollow structures. The second patterned arranged hollow structures have nano dimensions. The nitride semiconductor pillar layer is formed on the epitaxy substrate, and the nitride semiconductor layer is formed on the nitride semiconductor pillar layer. The mask layer covers surfaces of the nitride semiconductor pillar layer and the epitaxy substrate.

Abstract translation: 氮化物半导体衬底包括外延衬底，图案化氮化物半导体柱层，氮化物半导体层和掩模层。 氮化物半导体柱层包括多个第一图案化布置的中空结构和在第一图案化排列的中空结构之间形成的多个第二图案化布置的中空结构。 第二图案化排列的中空结构具有纳米尺寸。 在外延基板上形成氮化物半导体柱层，在氮化物半导体柱层上形成氮化物半导体层。 掩模层覆盖氮化物半导体柱层和外延基板的表面。