公开(公告)号：US11306529B2

公开(公告)日：2022-04-19

申请号：US16286625

申请日：2019-02-27

Applicant: Ruei-Hong Hong ,  Wen-Yi Chiu ,  Wei-Jun Wang ,  Po-Chun Liu

Inventor： Ruei-Hong Hong ,  Wen-Yi Chiu ,  Wei-Jun Wang ,  Po-Chun Liu

IPC: E05F15/73 ,  E05F15/77 ,  E06B9/24

Abstract: A space adjustment system and a control method thereof are provided. The space adjustment system includes a body, at least one door leaf, at least one motor, and a control circuit. The door leaf is movably disposed at the body. The door panel of each door leaf includes a panel. The motor can drive the motion of the door leaf. The control circuit is coupled with the panel of the door leaf and motor. The control circuit controls the motor to drive the door leaf, and adjusts the transparency or display function of the panel on the corresponding door leaf in response to a location of the door leaf. Accordingly, multiple space type can be created.

公开(公告)号：USD847958S1

公开(公告)日：2019-05-07

申请号：US29634803

申请日：2018-01-25

Applicant: Po-Chun Liu ,  Shi-Kuan Chen ,  Wei-Jun Wang ,  Wen-Yi Chiu ,  Ruei-Hong Hong

Designer： Po-Chun Liu ,  Shi-Kuan Chen ,  Wei-Jun Wang ,  Wen-Yi Chiu ,  Ruei-Hong Hong

公开(公告)号：US08912570B2

公开(公告)日：2014-12-16

申请号：US13571169

申请日：2012-08-09

Applicant: Chen-Hao Chiang ,  Han-Chin Chiu ,  Po-Chun Liu ,  Chi-Ming Chen ,  Chung-Yi Yu

Inventor： Chen-Hao Chiang ,  Han-Chin Chiu ,  Po-Chun Liu ,  Chi-Ming Chen ,  Chung-Yi Yu

IPC: H01L29/20

CPC classification number: H01L29/7784 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are in contact with the second III-V compound layer. A n-type doped region underlies each source feature and drain feature in the second III-V compound layer. A p-type doped region underlies each n-type doped region in the first III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the source feature and the drain feature.

Abstract translation: 高电子迁移率晶体管（HEMT）包括第一III-V族化合物层。 第二III-V化合物层设置在第一III-V化合物层上，并且与组合物中的第一III-V化合物层不同。 源特征和漏极特征与第二III-V复合层接触。 在第二III-V化合物层中的每个源特征和漏极特征的n型掺杂区域。 p型掺杂区域位于第一III-V化合物层中的每个n型掺杂区域的正下方。 栅电极设置在源特征和漏极特征之间的第二III-V化合物层的一部分上。

公开(公告)号：US20140042446A1

公开(公告)日：2014-02-13

申请号：US13571169

申请日：2012-08-09

Applicant: Chen-Hao Chiang ,  Han-Chin Chiu ,  Po-Chun Liu ,  Chi-Ming Chen ,  Chung-Yi Yu

Inventor： Chen-Hao Chiang ,  Han-Chin Chiu ,  Po-Chun Liu ,  Chi-Ming Chen ,  Chung-Yi Yu

IPC: H01L29/778 ,  H01L21/335 ,  H01L29/20

CPC classification number: H01L29/7784 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are in contact with the second III-V compound layer. A n-type doped region underlies each source feature and drain feature in the second III-V compound layer. A p-type doped region underlies each n-type doped region in the first III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the source feature and the drain feature.

Abstract translation: 高电子迁移率晶体管（HEMT）包括第一III-V族化合物层。 第二III-V化合物层设置在第一III-V化合物层上，并且与组合物中的第一III-V化合物层不同。 源特征和漏极特征与第二III-V复合层接触。 在第二III-V化合物层中的每个源特征和漏极特征的n型掺杂区域。 p型掺杂区域位于第一III-V化合物层中的每个n型掺杂区域的正下方。 栅电极设置在源特征和漏极特征之间的第二III-V化合物层的一部分上。

公开(公告)号：US20140001439A1

公开(公告)日：2014-01-02

申请号：US13534368

申请日：2012-06-27

Applicant: Chi-Ming Chen ,  Po-Chun Liu ,  Chung-Yi Yu

Inventor： Chi-Ming Chen ,  Po-Chun Liu ,  Chung-Yi Yu

IPC: H01L29/205 ,  H01L21/20

CPC classification number: B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/02458 ,  H01L21/02507 ,  H01L21/0251 ,  H01L21/0254 ,  H01L29/1075 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786

Abstract: The present disclosure is directed to an integrated circuit and a method for the fabrication of the integrated circuit. The integrated circuit includes a lattice matching structure. The lattice matching structure can include a first buffer region, a second buffer region and a superlattice structure formed from AlxGa1−xN/AlyGa1−yN layer pairs.

Abstract translation: 本公开涉及用于制造集成电路的集成电路和方法。 集成电路包括晶格匹配结构。 晶格匹配结构可以包括由Al x Ga 1-x N / Al y Ga 1-y N层对形成的第一缓冲区，第二缓冲区和超晶格结构。

公开(公告)号：US08221547B2

公开(公告)日：2012-07-17

申请号：US12177167

申请日：2008-07-22

Applicant: Po-Chun Liu ,  Yih-Der Guo ,  Tung-Wei Chi ,  Chu-Li Chao

Inventor： Po-Chun Liu ,  Yih-Der Guo ,  Tung-Wei Chi ,  Chu-Li Chao

IPC: B32B3/10 ,  C30B25/04

CPC classification number: C30B25/18 ,  C30B29/403 ,  Y10T428/24802 ,  Y10T428/24851

Abstract: An initial substrate structure for forming a nitride semiconductor substrate is provided. The initial substrate structure includes a substrate, a patterned epitaxial layer, and a mask layer. The patterned epitaxial layer is located on the substrate and is formed by a plurality of pillars. The mask layer is located over the substrate and covers a part of the patterned epitaxial layer. The mask layer includes a plurality of sticks and there is a space between the sticks. The space exposes a portion of an upper surface of the patterned epitaxial layer.

Abstract translation: 提供了用于形成氮化物半导体衬底的初始衬底结构。 初始衬底结构包括衬底，图案化外延层和掩模层。 图案化的外延层位于基板上并且由多个柱形成。 掩模层位于衬底上并覆盖图案化外延层的一部分。 掩模层包括多个棒，并且在棒之间存在空间。 空间暴露图案化外延层的上表面的一部分。

公开(公告)号：US20080272378A1

公开(公告)日：2008-11-06

申请号：US12137519

申请日：2008-06-11

Applicant: Yih-Der Guo ,  Chih-Ming Lai ,  Jenq-Dar Tsay ,  Po-Chun Liu

Inventor： Yih-Der Guo ,  Chih-Ming Lai ,  Jenq-Dar Tsay ,  Po-Chun Liu

IPC: H01L29/15 ,  H01L21/31

CPC classification number: C30B25/02 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/0254 ,  H01L21/0265 ,  H01L21/02664 ,  H01L33/0079

Abstract: There is provided a method of forming a nitride semiconductor layer, including the steps of firstly providing a substrate on which a patterned epitaxy layer with a pier structure is formed. A protective layer is then formed on the patterned epitaxy layer, exposing a top surface of the pier structure. Next, a nitride semiconductor layer is formed over the patterned epitaxy layer connected to the nitride semiconductor layer through the pier structure, wherein the nitride semiconductor layer, the pier structure, and the patterned epitaxy layer together form a space exposing a bottom surface of the nitride semiconductor layer. Thereafter, a weakening process is performed to remove a portion of the bottom surface of the nitride semiconductor layer and to weaken a connection point between the top surface of the pier structure and the nitride semiconductor layer. Finally, the substrate is separated from the nitride semiconductor layer through the connection point.

Abstract translation: 提供一种形成氮化物半导体层的方法，包括以下步骤：首先提供其上形成有墩结构的图案化外延层的基板。 然后在图案化的外延层上形成保护层，露出墩结构的顶表面。 接下来，在通过墩结构连接到氮化物半导体层的图案化外延层上形成氮化物半导体层，其中氮化物半导体层，墩结构和图案化外延层一起形成暴露氮化物的底表面的空间 半导体层。 此后，执行弱化处理以去除氮化物半导体层的底表面的一部分并削弱墩结构的顶表面和氮化物半导体层之间的连接点。 最后，通过连接点将衬底与氮化物半导体层分离。

公开(公告)号：US20080054293A1

公开(公告)日：2008-03-06

申请号：US11562421

申请日：2006-11-22

Applicant: Chih-Ming Lai ,  Po-Chun Liu

Inventor： Chih-Ming Lai ,  Po-Chun Liu

IPC: H01L33/00

CPC classification number: C30B25/02 ,  C30B25/18 ,  C30B29/403 ,  H01L21/0237 ,  H01L21/0254 ,  H01L21/02639 ,  H01L21/02647

Abstract: A method of manufacturing a nitride semiconductor substrate is provided. A partial surface treatment process is performed to rough a portion of a surface of a substrate. Next, a nitride semiconductor layer is formed over the substrate. Since the nitride semiconductor layer simply grows on the unroughened surface of the substrate through selective area epitaxy growth and lateral epitaxy growth, some of the threading dislocations in the nitride semiconductor layer are blocked. Thereby, the threading dislocation density of the grown nitride semiconductor layer is reduced.

Abstract translation: 提供一种制造氮化物半导体衬底的方法。 进行部分表面处理工艺以粗糙化衬底表面的一部分。 接下来，在衬底上形成氮化物半导体层。 由于氮化物半导体层通过选择性区域外延生长和横向外延生长简单地在衬底的未粗化表面上生长，所以氮化物半导体层中的一些穿透位错被阻挡。 因此，生长的氮化物半导体层的穿透位错密度降低。

公开(公告)号：US20220245864A1

公开(公告)日：2022-08-04

申请号：US17586714

申请日：2022-01-27

Applicant: Yi-Ching Tu ,  Po-Chun Liu ,  Kai-Yu Lei ,  Dai-Yun Tsai

Inventor： Yi-Ching Tu ,  Po-Chun Liu ,  Kai-Yu Lei ,  Dai-Yun Tsai

IPC: G06T11/00 ,  G06T7/20 ,  G06T7/73 ,  G06V40/10 ,  H04N5/265

Abstract: A generating method of conference image and an image conference system are provided. In the method, a user and one or more tags in a captured actual image are identified. The moving behavior of the user is tracked, and the position of the viewing range in the actual image is adjusted according to the moving behavior. The virtual image corresponding to the tag is synthesized according to the position relation between the user and the tag, to generate a conference image.

公开(公告)号：US11208793B2

公开(公告)日：2021-12-28

申请号：US16658183

申请日：2019-10-21

Applicant: Po-Chun Liu ,  Wen-Yi Chiu ,  Pin-Hsing Lee

Inventor： Po-Chun Liu ,  Wen-Yi Chiu ,  Pin-Hsing Lee

IPC: E03C1/048 ,  E03C1/05 ,  E03C1/046 ,  E03C1/044 ,  E03C1/10 ,  E03C1/04 ,  C02F1/32

Abstract: A sanitary equipment with a water supply system, a water route system, and a hand washing table are provided. The sanitary equipment includes a machine having a machine water outlet; a movable hand washing table pivoted on the machine and located below the machine water outlet, the movable hand washing table being capable of opening or retracting with respect to the machine; and a water route system disposed in the machine and connected to the machine water outlet to discharge potable water and non-potable water from the machine water outlet.