公开(公告)号：US20140209919A1

公开(公告)日：2014-07-31

申请号：US13753867

申请日：2013-01-30

Applicant: Han-Chin CHIU ,  Chen-Hao CHIANG ,  Chi-Ming CHEN ,  Chung-Yi YU

Inventor： Han-Chin CHIU ,  Chen-Hao CHIANG ,  Chi-Ming CHEN ,  Chung-Yi YU

IPC: H01L29/66 ,  H01L29/20

CPC classification number: H01L29/42364 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: A method including forming a III-V compound layer on a substrate and implanting a main dopant in the III-V compound layer to form source and drain regions. The method further includes implanting a group V species into the source and drain regions. A semiconductor device including a substrate and a III-V compound layer over the substrate. The semiconductor device further includes source and drain regions in the III-V layer, wherein the source and drain regions comprises a first dopant and a second dopant, and the second dopant comprises a group V material.

Abstract translation: 一种方法，包括在衬底上形成III-V化合物层并在III-V化合物层中注入主掺杂剂以形成源区和漏区。 该方法还包括将V族物质注入源区和漏区。 一种半导体器件，包括在衬底上的衬底和III-V化合物层。 半导体器件还包括III-V层中的源区和漏区，其中源区和漏区包括第一掺杂剂和第二掺杂剂，第二掺杂剂包括第V族材料。

公开(公告)号：US08912570B2

公开(公告)日：2014-12-16

申请号：US13571169

申请日：2012-08-09

Applicant: Chen-Hao Chiang ,  Han-Chin Chiu ,  Po-Chun Liu ,  Chi-Ming Chen ,  Chung-Yi Yu

Inventor： Chen-Hao Chiang ,  Han-Chin Chiu ,  Po-Chun Liu ,  Chi-Ming Chen ,  Chung-Yi Yu

IPC: H01L29/20

CPC classification number: H01L29/7784 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are in contact with the second III-V compound layer. A n-type doped region underlies each source feature and drain feature in the second III-V compound layer. A p-type doped region underlies each n-type doped region in the first III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the source feature and the drain feature.

Abstract translation: 高电子迁移率晶体管（HEMT）包括第一III-V族化合物层。 第二III-V化合物层设置在第一III-V化合物层上，并且与组合物中的第一III-V化合物层不同。 源特征和漏极特征与第二III-V复合层接触。 在第二III-V化合物层中的每个源特征和漏极特征的n型掺杂区域。 p型掺杂区域位于第一III-V化合物层中的每个n型掺杂区域的正下方。 栅电极设置在源特征和漏极特征之间的第二III-V化合物层的一部分上。

公开(公告)号：US20140042446A1

公开(公告)日：2014-02-13

申请号：US13571169

申请日：2012-08-09

Applicant: Chen-Hao Chiang ,  Han-Chin Chiu ,  Po-Chun Liu ,  Chi-Ming Chen ,  Chung-Yi Yu

Inventor： Chen-Hao Chiang ,  Han-Chin Chiu ,  Po-Chun Liu ,  Chi-Ming Chen ,  Chung-Yi Yu

IPC: H01L29/778 ,  H01L21/335 ,  H01L29/20

CPC classification number: H01L29/7784 ,  H01L29/0891 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7787

Abstract: A high electron mobility transistor (HEMT) includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and is different from the first III-V compound layer in composition. A source feature and a drain feature are in contact with the second III-V compound layer. A n-type doped region underlies each source feature and drain feature in the second III-V compound layer. A p-type doped region underlies each n-type doped region in the first III-V compound layer. A gate electrode is disposed over a portion of the second III-V compound layer between the source feature and the drain feature.

Abstract translation: 高电子迁移率晶体管（HEMT）包括第一III-V族化合物层。 第二III-V化合物层设置在第一III-V化合物层上，并且与组合物中的第一III-V化合物层不同。 源特征和漏极特征与第二III-V复合层接触。 在第二III-V化合物层中的每个源特征和漏极特征的n型掺杂区域。 p型掺杂区域位于第一III-V化合物层中的每个n型掺杂区域的正下方。 栅电极设置在源特征和漏极特征之间的第二III-V化合物层的一部分上。

公开(公告)号：US20140014967A1

公开(公告)日：2014-01-16

申请号：US13549610

申请日：2012-07-16

Applicant: Chi-Ming Chen ,  Han-Chin Chiu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

Inventor： Chi-Ming Chen ,  Han-Chin Chiu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC: H01L29/267 ,  H01L21/20

CPC classification number: H01L21/02381 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786

Abstract: The present disclosure is directed to an integrated circuit and its formation. In some embodiments, the integrated circuit includes a diffusion barrier layer. The diffusion barrier layer can be arranged to prevent diffusion of the Si and O2 from a Si substrate into a Group III nitride layer. The diffusion barrier layer can comprise Al2O3. In some embodiments, the integrated circuit further comprises a lattice-matching structure disposed between the silicon substrate and a Group III nitride layer.

Abstract translation: 本公开涉及集成电路及其形成。 在一些实施例中，集成电路包括扩散阻挡层。 扩散阻挡层可以被布置成防止Si和O 2从Si衬底扩散到III族氮化物层中。 扩散阻挡层可以包括Al 2 O 3。 在一些实施例中，集成电路还包括设置在硅衬底和III族氮化物层之间的晶格匹配结构。

公开(公告)号：US08884268B2

公开(公告)日：2014-11-11

申请号：US13549610

申请日：2012-07-16

Applicant: Chi-Ming Chen ,  Han-Chin Chiu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

Inventor： Chi-Ming Chen ,  Han-Chin Chiu ,  Chung-Yi Yu ,  Chia-Shiung Tsai

IPC: H01L21/44

CPC classification number: H01L21/02381 ,  H01L21/02458 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/0251 ,  H01L21/0254 ,  H01L29/2003 ,  H01L29/66462 ,  H01L29/7786

Abstract: The present disclosure is directed to an integrated circuit and its formation. In some embodiments, the integrated circuit includes a diffusion barrier layer. The diffusion barrier layer can be arranged to prevent diffusion of the Si and O2 from a Si substrate into a Group III nitride layer. The diffusion barrier layer can comprise Al2O3. In some embodiments, the integrated circuit further comprises a lattice-matching structure disposed between the silicon substrate and a Group III nitride layer.

Abstract translation: 本公开涉及集成电路及其形成。 在一些实施例中，集成电路包括扩散阻挡层。 扩散阻挡层可以被布置成防止Si和O 2从Si衬底扩散到III族氮化物层中。 扩散阻挡层可以包括Al 2 O 3。 在一些实施例中，集成电路还包括设置在硅衬底和III族氮化物层之间的晶格匹配结构。