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公开(公告)号：US20240005986A1
公开(公告)日：2024-01-04
申请号：US17993586
申请日：2022-11-23
申请人： William Robert Reohr
发明人： William Robert Reohr
IPC分类号： G11C11/44 , G11C7/12 , H03K3/38 , H03K19/195
CPC分类号： G11C11/44 , G11C7/12 , H03K3/38 , H03K19/1952
摘要： A superconducting distributed bidirectional current driver system includes multiple bidirectional current drivers, a bidirectional current load being operatively coupled between two adjacent bidirectional current drivers. Each of the bidirectional current drivers includes first and second superconducting latch circuits. The first superconducting latch circuit in a first one of the bidirectional current drivers and the second superconducting latch circuit in a second one of the bidirectional current drivers coupled to the current load are selectively activated by first and second activation signals, respectively, to establish a first current path through the current load in a first direction. The second superconducting latch circuit in the second one of the bidirectional current drivers and the first superconducting latch circuit in the first one of the bidirectional current drivers are selectively activated to establish a second current path through the current load in a second direction opposite the first direction.
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公开(公告)号：US20240005968A1
公开(公告)日：2024-01-04
申请号：US17993543
申请日：2022-11-23
CPC分类号： G11C7/1066 , G11C7/1063 , G11C7/1096 , G11C11/44
摘要： A memory output circuit for selectively propagating proximate memory output data in a memory array of superconducting memory cells includes multiple datum inputs adapted to operably receive corresponding memory state signals from physically adjacent bit lines in the memory array, and at least one logic gate configured to implement logical OR functionality. The logic gate includes multiple inputs, for receiving at least a subset of the datum inputs operatively coupled thereto, and an output for propagating at least one datum output signal. The memory output circuit further includes at least one delay element operatively coupled to a corresponding one of the datum inputs. The delay element is configured to generate an output signal operably connected to a corresponding one of the inputs of the logic gate, the output signal generated by the delay element being a temporal sequence of at least a subset of the memory state signals supplied thereto delayed by a prescribed delay value.
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公开(公告)号：US20230136455A1
公开(公告)日：2023-05-04
申请号：US17976179
申请日：2022-10-28
申请人： William Robert Reohr
发明人： William Robert Reohr
IPC分类号： G11C11/44
摘要： A superconducting memory circuit for applying and propagating superconducting signals through a plurality of superconducting wires in the memory circuit is provided. The memory circuit includes multiple passive cells arranged in a plurality of sets. Each set of passive cells has associated therewith at least one common superconducting wire interconnecting a subset of the passive cells in the set of passive cells. The memory circuit further including at least one power-signal propagation circuit, an input of the power-signal propagation circuit being coupled with a preceding set of passive cells via a first superconducting wire, and an output of the power-signal propagation circuit being coupled with a subsequent set of passive cells via a second superconducting wire. Upon application of a first superconducting signal to the first superconducting wire, the power-signal propagation circuit applies a second superconducting signal to the second superconducting wire.
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公开(公告)号：US10447278B1
公开(公告)日：2019-10-15
申请号：US16037587
申请日：2018-07-17
IPC分类号： H03K19/195 , H03K19/177 , G06N10/00 , G11C11/44
摘要： Superconducting logic arrays (SLAs) and field-programmable gate arrays (FPGAs) that are based on Josephson transmission lines (JTLs) accommodate reciprocal quantum logic (RQL) compliant binary input signals and provide RQL-compliant output signals that are evaluations of generalized logic functions. Each JTL-based superconducting FPGA (JTLBSFPGA) incorporates multiple JTL-based SLAs (JTLBSLAs) connected together. Each JTLBSLA includes an array of software-programmable and/or mask-programmed logic cells that output products of inputs and cell states, such that the JTLBSLAs output evaluations of sum-of-products functions. New JTLBSLA logic cells are described, including some that provide programmable cell states via magnetic Josephson junctions (MJJs). JTLBSFPGAs provide area efficiency and clock speed advantages over CMOS FPGAs. Unlike SLAs based on Josephson magnetic random access memory (JMRAM), JTLBSLAs do not require word line drivers, flux pumps, or sense amplifiers. Because JTLBSLAs and JTLBSFPGAs are RQL-compliant, they can also include RQL gates connected within or between them, without signal conversion circuitry.
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公开(公告)号：US09384827B1
公开(公告)日：2016-07-05
申请号：US14639688
申请日：2015-03-05
申请人： William Robert Reohr , Steven Brian Shauck , Donald Lynn Miller , Jeremy William Horner , Nathan Trent Josephsen
发明人： William Robert Reohr , Steven Brian Shauck , Donald Lynn Miller , Jeremy William Horner , Nathan Trent Josephsen
CPC分类号： G11C11/44 , B82Y10/00 , B82Y20/00 , B82Y25/00 , G11C7/12 , G11C7/22 , G11C8/04 , G11C8/18 , G11C11/16 , G11C11/1655 , G11C11/1657 , G11C11/1659 , G11C11/1693 , G11C19/32
摘要： One embodiment describes a quantum memory system. The system includes a plurality of quantum memory cells arranged in an array of rows and columns. Each of the plurality of quantum memory cells can be configured to store a binary logic state in response to write currents in a write operation and configured to provide an indication of the binary logic state in response to read currents in a read operation. The system also includes an array controller comprising a plurality of flux pumps configured to provide the write currents and the read currents with respect to the rows and columns. The array controller can be configured to control timing associated with the write operation and the read operation in response to memory request signals based on application of the write currents and the read currents and based on recharging flux associated with the plurality of flux pumps.
摘要翻译： 一个实施例描述了量子存储器系统。 该系统包括以行和列阵列排列的多个量子存储单元。 多个量子存储器单元中的每一个可以被配置为响应于写入操作中的写入电流来存储二进制逻辑状态，并且被配置为响应读取操作中的读取电流来提供二进制逻辑状态的指示。 该系统还包括阵列控制器，该阵列控制器包括被配置为相对于行和列提供写入电流和读取电流的多个磁通泵。 阵列控制器可以被配置为基于写入电流和读取电流的应用以及基于与多个磁通泵相关联的再充电通量来响应于存储器请求信号来控制与写入操作和读取操作相关联的定时。
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公开(公告)号：US20130135941A1
公开(公告)日：2013-05-30
申请号：US13307884
申请日：2011-11-30
IPC分类号： G11C7/10 , G11C11/402 , G11C7/00
CPC分类号： G11C11/4085 , G11C11/406 , G11C11/4072 , G11C11/4074 , G11C11/4094
摘要： A memory device includes memory cells, each of the memory cells having corresponding bit and word lines connected thereto for accessing the memory cells, a word line circuit coupled with at least one word line, and a bit line circuit coupled with at least one bit line. The memory device further includes at least one control circuit coupled with the bit and word line circuits. The control circuit is operative to cause state information to be stored in the memory cells. At least one switching element selectively connects the memory cells, the bit and word line circuits, and the control circuit to at least one power supply as a function of at least one control signal. The control circuit generates the control signal for disconnecting at least portions of the word line and bit line circuits from the power supply while state information is retained in the memory cells.
摘要翻译： 存储器件包括存储器单元，每个存储器单元具有连接到其上的相应位和字线用于访问存储器单元，与至少一个字线耦合的字线电路和与至少一个位线耦合的位线电路 。 存储器件还包括与位和字线电路耦合的至少一个控制电路。 控制电路用于使状态信息存储在存储单元中。 至少一个开关元件将存储器单元，位和字线电路以及控制电路选择性地连接到作为至少一个控制信号的函数的至少一个电源。 控制电路产生控制信号，用于将字线和位线电路的至少一部分与电源断开，同时将状态信息保留在存储单元中。
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公开(公告)号：US20100054057A1
公开(公告)日：2010-03-04
申请号：US12199438
申请日：2008-08-27
CPC分类号： G11C11/4091 , G11C11/4097
摘要： Techniques for sensing data states of respective memory cells in a memory array are provided, the memory array including at least a first bit line coupled to at least a subset of the memory cells. In one aspect, a circuit for sensing data states of respective memory cells in the memory array includes at least one sense amplifier coupled to the first bit line. The sense amplifier includes a first transistor operative to selectively inhibit charging of the first bit line in a manner which is independent of a voltage level on a second bit line coupled to the sense amplifier.
摘要翻译： 提供了用于感测存储器阵列中的相应存储器单元的数据状态的技术，所述存储器阵列至少包括耦合到所述存储器单元的至少一个子集的第一位线。 在一个方面，用于感测存储器阵列中各个存储单元的数据状态的电路包括耦合到第一位线的至少一个读出放大器。 感测放大器包括第一晶体管，其操作以选择性地禁止第一位线的充电，其方式与在与读出放大器耦合的第二位线上的电压电平无关。
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公开(公告)号：US20080313407A1
公开(公告)日：2008-12-18
申请号：US11762358
申请日：2007-06-13
申请人： Zhigang Hu , William Robert Reohr
发明人： Zhigang Hu , William Robert Reohr
IPC分类号： G06F13/00
CPC分类号： G06F12/127 , G06F12/0811 , G06F12/084 , G06F12/0864 , G06F2212/271
摘要： A method for replacing cache lines in a computer system having a non-uniform set associative cache memory is disclosed. The method incorporates access latency as an additional factor into the existing ranking guidelines for replacement of a line, the higher the rank of the line the sooner that it is likely to be evicted from the cache. Among a group of highest ranking cache lines in a cache set, the cache line chosen to be replaced is one that provides the lowest latency access to a requesting entity, such as a processor. The distance separating the requesting entity from the memory partition where the cache line is stored most affects access latency.
摘要翻译： 公开了一种用于替换具有非均匀集合关联高速缓冲存储器的计算机系统中的高速缓存行的方法。 该方法将访问延迟作为替代线路的现有排名指南的附加因素，该行的排名越高，越可能从缓存中逐出。 在缓存集中的一组最高排名的高速缓存行中，选择要替换的高速缓存行是为请求实体（例如处理器）提供最低延迟访问的高速缓存行。 将请求实体与存储高速缓存行存储的内存分区分开的距离最大程度上影响访问延迟。
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9.发明申请公开(公告)号：US20080263383A1
公开(公告)日：2008-10-23
申请号：US12163493
申请日：2008-06-27
IPC分类号： G06F1/04
CPC分类号： G06F11/008
摘要： A number of performance parameters for the electronic system are determined at a particular age of the electronic system. The performance parameters can be correlated to maximum operating frequency of electronic components of the electronic system for the particular age of the electronic system. Operating frequency of the electronic components is adjusted in accordance with the performance parameters. The performance parameters may be predetermined (such as through reliability and burn-in testing), determined during the life of the electronic system, or some combination of these. Performance parameters can comprise prior operating frequencies, hours of operation, ambient temperature, and supply voltage. Performance parameters can comprise performance statistics determined using age-monitoring circuits, where an aged circuit is compared with a circuit enabled only for comparison. Performance statistics may also be determined though error detection circuits. If an error is detected, the operating frequency can be reduced.
摘要翻译： 在电子系统的特定年龄确定电子系统的许多性能参数。 性能参数可以与电子系统的特定年龄的电子系统的电子部件的最大工作频率相关联。 电子元件的工作频率根据性能参数进行调整。 性能参数可以是预定的（例如通过可靠性和老化测试），在电子系统的寿命期间确定，或者这些的一些组合。 性能参数可以包括以前的工作频率，工作时间，环境温度和电源电压。 性能参数可以包括使用年龄监测电路确定的性能统计，其中老化电路与仅用于比较的电路进行比较。 也可以通过错误检测电路来确定性能统计。 如果检测到错误，则可以减少工作频率。
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公开(公告)号：US20080175085A1
公开(公告)日：2008-07-24
申请号：US12057011
申请日：2008-03-27
IPC分类号： G11C7/06
CPC分类号： G11C7/12 , G11C7/02 , G11C7/062 , G11C11/4091 , G11C11/4094
摘要： A memory circuit includes multiple word lines, multiple pairs of complementary bank bit lines, multiple block select lines, and multiple of block circuits. Each of the block circuits includes a local bit line; a first transistor having a control terminal connected to the local bit line, a first bias terminal connected to a first bank bit line of a given pair of bank bit lines, and a second bias terminal connecting to a first voltage source; a second transistor having a control terminal connected to a corresponding one of the block select lines, a first bias terminal connected to a second bank bit line of the given pair of bank bit lines, and a second bias terminal connected to the local bit line; and a plurality of memory cells connected to the local bit line and to respective word lines in the memory circuit. At least two block circuits are connected to a given pair of bank bit lines, the block circuits being configured such that a load on each bank bit line in the given pair of bank bit lines is substantially matched to one another.
摘要翻译： 存储器电路包括多个字线，多对互补组位线，多个块选择线和多个块电路。 每个块电路包括局部位线; 第一晶体管，其具有连接到本地位线的控制端子，连接到给定的一对组位线的第一组位线的第一偏置端子和连接到第一电压源的第二偏置端子; 第二晶体管，其具有连接到对应的一个块选择线的控制端子，连接到给定的一对组位线的第二组位线的第一偏置端子和连接到局部位线的第二偏置端子; 以及连接到本地位线和存储电路中的相应字线的多个存储单元。 至少两个块电路连接到给定的一组组位线，块电路被配置为使得给定的一组组位线中的每个组位线上的负载基本上彼此匹配。
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