公开(公告)号：US08519735B2

公开(公告)日：2013-08-27

申请号：US13217734

申请日：2011-08-25

申请人： Liang-Teck Pang ,  Joel A. Silberman ,  Matthew R. Wordeman

发明人： Liang-Teck Pang ,  Joel A. Silberman ,  Matthew R. Wordeman

IPC分类号： H03K19/00

CPC分类号： G01R31/318558 ,  G01R31/318513 ,  G01R31/318572 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a strata manager within a 3D chip stack having two or more strata. The strata manager includes a plurality of scannable configuration registers, each being arranged on a respective one of the two or more strata for storing a set of bits. The set of bits is configured to program an operation of a corresponding one of the two or more strata on which the set of bits is stored or a device thereon. Additionally, a stratum identifier within a 3D stack and stack-wide scan circuit within a 3D stack are provided.

公开(公告)号：US20130055183A1

公开(公告)日：2013-02-28

申请号：US13217381

申请日：2011-08-25

申请人： MICHAEL P. BEAKES ,  SHIH-HSIEN LO ,  MICHAEL R. SCHEUERMANN ,  MATTHEW R. WORDEMAN

发明人： MICHAEL P. BEAKES ,  SHIH-HSIEN LO ,  MICHAEL R. SCHEUERMANN ,  MATTHEW R. WORDEMAN

IPC分类号： G06F17/50

CPC分类号： G06F17/5081 ,  G06F2217/40 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a method for verifying inter-stratum connectivity for two or more strata to be combined into a 3D chip stack. Each of the two or more strata has 3D elements including active 3D elements, mechanical 3D elements, and dummy 3D elements. The method includes performing a respective 2D layout versus schematic verification on each of the two or more strata with respect to at least the 3D elements to pre-ensure an absence of shorts between the 3D elements when the two or more strata are subsequently stacked into the 3D chip stack. The method further includes checking inter-stratum interconnectivity between each adjacent pair of strata in the 3D chip stack.

摘要翻译： 提供了一种用于验证要组合成3D芯片堆栈的两个或更多个层的层间连通性的方法。 两个或更多个层中的每一个具有包括主动3D元素，机械3D元素和虚拟3D元素的3D元素。 该方法包括相对于至少3D元件在两个或更多个层中的每一个上执行相应的2D布局，以相对于示意图验证，以便当两个或更多个层随后被堆叠到3D元素中时预先确保在3D元件之间不存在短路 3D芯片堆栈。 该方法还包括检查3D芯片堆叠中每个相邻层之间的层间互连性。

公开(公告)号：US20120171819A1

公开(公告)日：2012-07-05

申请号：US13417444

申请日：2012-03-12

申请人： Leland Chang ,  Matthew R. Wordeman ,  Albert M. Young

发明人： Leland Chang ,  Matthew R. Wordeman ,  Albert M. Young

IPC分类号： H01L21/50

CPC分类号： H01L25/0657 ,  H01L23/5252 ,  H01L23/5256 ,  H01L24/06 ,  H01L24/14 ,  H01L24/16 ,  H01L25/50 ,  H01L2224/0401 ,  H01L2224/05555 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/05684 ,  H01L2224/13099 ,  H01L2225/06513 ,  H01L2225/06527 ,  H01L2225/06541 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/00014

摘要： An array of contact pads on a semiconductor structure has a pitch less than twice an overlay tolerance of a bonding process employed to vertically stack semiconductor structures. A set of contact pads within the area of overlay variation for a matching contact pin may be electrically connected to an array of programmable contacts such that one programmable contact is connected to each contact pad within the area of overlay variation. One contact pad may be provided with a plurality of programmable contacts. The variability of contacts between contact pins and contact pads is accommodated by connecting or disconnecting programmable contacts after the stacking of semiconductor structures. Since the pitch of the array of contact pins may be less than twice the overlay variation of the bonding process, a high density of interconnections is provided in the vertically stacked structure.

摘要翻译： 半导体结构上的接触焊盘阵列的间距小于用于垂直堆叠半导体结构的接合工艺的覆盖公差的两倍。 用于匹配接触针的覆盖变化区域内的一组接触焊盘可以电连接到可编程触点阵列，使得一个可编程触点连接到覆盖变化区域内的每个接触焊盘。 一个接触垫可以设置有多个可编程触点。 在半导体结构堆叠之后，通过连接或断开可编程触点来容纳接触引脚和接触焊盘之间的接触的可变性。 由于接触引脚阵列的间距可能小于接合过程的覆盖变化的两倍，所以垂直堆叠结构中提供了高密度的互连。

公开(公告)号：US07545667B2

公开(公告)日：2009-06-09

申请号：US11393270

申请日：2006-03-30

申请人： Bruce G. Elmegreen ,  Lia Krusin-Elbaum ,  Chung Hon Lam ,  Dennis M. Newns ,  Matthew R. Wordeman ,  Albert M. Young

发明人： Bruce G. Elmegreen ,  Lia Krusin-Elbaum ,  Chung Hon Lam ,  Dennis M. Newns ,  Matthew R. Wordeman ,  Albert M. Young

IPC分类号： G11C11/00

CPC分类号： H01L45/144 ,  H01L23/5226 ,  H01L23/5252 ,  H01L23/5256 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/122 ,  H01L45/1226 ,  H01L45/1286 ,  H01L2924/0002 ,  H01L2924/00

摘要： A programmable link structure for use in three dimensional integration (3DI) semiconductor devices includes a via filled at least in part with a phase change material (PCM) and a heating device proximate the PCM. The heating device is configured to switch the conductivity of a transformable portion of the PCM between a lower resistance crystalline state and a higher resistance amorphous state. Thereby, the via defines a programmable link between an input connection located at one end thereof and an output connection located at another end thereof.

摘要翻译： 用于三维积分（3DI）半导体器件的可编程链路结构包括至少部分地填充有相变材料（PCM）和靠近PCM的加热装置的通孔。 加热装置被配置为将PCM的可变形部分的电导率切换到较低电阻结晶状态和较高电阻无定形状态。 因此，通路限定位于其一端的输入连接与位于其另一端的输出连接之间的可编程连接。

公开(公告)号：US20080268574A1

公开(公告)日：2008-10-30

申请号：US12035053

申请日：2008-02-21

申请人： Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornelia K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

发明人： Kuan-Neng Chen ,  Bruce K. Furman ,  Edmund J. Sprogis ,  Anna W. Topol ,  Cornelia K. Tsang ,  Matthew R. Wordeman ,  Albert M. Young

IPC分类号： H01L21/58

CPC分类号： H01L25/50 ,  H01L2224/80895 ,  H01L2225/06513 ,  H01L2225/06593 ,  H01L2924/0002 ,  H01L2924/00

摘要： A sealed microelectronic structure which provides mechanical stress endurance and includes at least two chips being electrically connected to a semiconductor structure at a plurality of locations. Each chip includes a continuous bonding material along it's perimeter and at least one support column connected to each of the chips positioned within the perimeter of each chip. Each support column extends outwardly such that when the at least two chips are positioned over one another the support columns are in mating relation to each other. A seal between the at least two chips results from the overlapping relation of the chip to one another such that the bonding material and support columns are in mating relation to each other. Thus, the seal is formed when the at least two chips are mated together, and results in a bonded chip structure.

摘要翻译： 一种密封的微电子结构，其提供机械应力耐久性并且包括在多个位置处电连接到半导体结构的至少两个芯片。 每个芯片沿着其周边包括连续的接合材料，以及连接到位于每个芯片的周边内的每个芯片的至少一个支撑柱。 每个支撑柱向外延伸，使得当至少两个芯片彼此定位时，支撑柱彼此配合。 至少两个芯片之间的密封由芯片彼此的重叠关系产生，使得接合材料和支撑柱彼此配合。 因此，当至少两个芯片配合在一起时形成密封，并且导致粘合芯片结构。

公开(公告)号：US07194670B2

公开(公告)日：2007-03-20

申请号：US10708184

申请日：2004-02-13

申请人： Jonathan R. Fales ,  Gregory J. Fredeman ,  Kevin W. Gorman ,  Mark D. Jacunski ,  Toshiaki Kirihata ,  Alan D. Norris ,  Paul C. Parries ,  Matthew R. Wordeman

发明人： Jonathan R. Fales ,  Gregory J. Fredeman ,  Kevin W. Gorman ,  Mark D. Jacunski ,  Toshiaki Kirihata ,  Alan D. Norris ,  Paul C. Parries ,  Matthew R. Wordeman

IPC分类号： G01R31/28

CPC分类号： G11C29/16 ,  G11C29/12015 ,  G11C29/14 ,  G11C2029/0401

摘要： Disclosed is a flexible command multiplication scheme for the built-in-self test (BIST) of a high-speed embedded memory array that segments BIST functionality into remote lower-speed executable instructions and local higher-speed executable instructions. A stand-alone BIST logic controller operates at a lower frequency and communicates with a command multiplier using a low-speed BIST instruction seed set. The command multiplier uses offset or directive registers to drive a logic unit or ALU to generate “n” sets of CAD information which are then time-multiplexed to the embedded memory at a speed “n” times faster than the BIST operating speed.

摘要翻译： 公开了用于高速嵌入式存储器阵列的内置自检（BIST）的灵活的命令乘法方案，其将BIST功能分段成远程低速可执行指令和本地较高速可执行指令。 独立的BIST逻辑控制器以较低的频率工作，并与使用低速BIST指令种子集的命令乘法器进行通信。 命令乘法器使用偏移或指令寄存器来驱动逻辑单元或ALU以产生“n”组CAD信息，然后以比BIST操作速度快n倍的速度将时间复用到嵌入式存储器。

公开(公告)号：US06343044B1

公开(公告)日：2002-01-29

申请号：US09679124

申请日：2000-10-04

申请人： Louis Lu-Chen Hsu ,  Richard Michael Parent ,  Matthew R. Wordeman

发明人： Louis Lu-Chen Hsu ,  Richard Michael Parent ,  Matthew R. Wordeman

IPC分类号： G11C700

CPC分类号： G11C11/406 ,  G11C5/146 ,  G11C8/08 ,  G11C11/4074 ,  G11C2207/104

摘要： A system and method for considerable reduction of power consumption in memory circuits implementing Vbb (array body bias) and Vwl (negative word line) voltage generators. The system comprises switching off the negative WL generator during sleep or standby mode, so that no power is consumed. A relaxed refresh operation is carried out and the negative WL is powered by the Vbb generator. The noise coupled to the negative WL supply from BL swing is reduced due to the joint Vbb-Vwl decoupling scheme. In the active mode, the Vbb and Vneg are separated to avoid any cross-over noise and to maintain design flexibility. During power-on period, the ramp-up rate of Vbb level is improved by the Vwl generator. The advantages may be summarized as: (1) simpler Vbb generator design, (2) much smaller Vbb generator size, (3) reduced Vbb power, (4) no stand-by current from Vwl generator, (5) low decoupling noise for Vwl level during stand-by or sleep mode, (6) enhanced ramp-up rate for Vbb during power-on, (7) no cross-over noise between Vbb and Vwl during active mode, and (8) design flexibility of Vbb and Vwl in the active mode. The principles and advantages of the invention may be applied to any two or more DC generator systems, negative or positive.

摘要翻译： 用于实现Vbb（阵列体偏置）和Vwl（负字线）电压发生器的存储电路中的功耗的显着降低的系统和方法。 该系统包括在睡眠或待机模式期间关闭负WL发生器，使得不消耗电力。 执行松弛的刷新操作，负的WL由Vbb发生器供电。 由于联合Vbb-Vwl去耦方案，耦合到BL摆幅的负WL电源的噪声减小。 在活动模式下，Vbb和Vneg被分离，以避免任何交叉噪声并保持设计灵活性。 在上电期间，Vwl发生器提高了Vbb电平的上升速率。 其优点可概括为：（1）Vbb发电机设计更简单，（2）Vbb发电机尺寸小得多，（3）Vbb功率降低，（4）Vwl发电机无待机电流，（5）低去耦噪声 待机或休眠模式下的Vwl电平，（6）上电期间Vbb的提升速率，（7）在活动模式期间Vbb和Vwl之间没有交叉噪声，（8）Vbb和Vbb的设计灵活性 Vwl处于活动模式。 本发明的原理和优点可以应用于任何两个或多个DC发电机系统，负极或正极。

公开(公告)号：US5389567A

公开(公告)日：1995-02-14

申请号：US241136

申请日：1994-05-10

申请人： Alexandre Acovic ,  Ching-Hsiang Hsu ,  Matthew R. Wordeman ,  Being S. Wu

发明人： Alexandre Acovic ,  Ching-Hsiang Hsu ,  Matthew R. Wordeman ,  Being S. Wu

IPC分类号： H01L27/105 ,  G11B17/028 ,  G11C14/00 ,  H01L21/8247 ,  H01L29/788 ,  H01L29/792 ,  H01L21/70

CPC分类号： B82Y10/00 ,  G11C14/00

摘要： The present invention is directed to a one-transistor non-volatile DRAM cell having a two layer floating gate to allow the contents of a storage capacitor to be transferred to the floating gate during power interruptions. The first layer of the floating gate is separated from a storage node of the storage capacitor by a tunnel oxide to allow electron tunnelling between the floating gate and the storage capacitor. In another embodiment of the present invention, a dual electron injector structure is disposed between a one layer floating and the storage node to allow electrons to be injected between the floating gate and the storage node. In another embodiment of the present invention, an erase gate is implemented to remove the charge on the floating gate. The erase gate can be separated from the floating gate by a tunnel oxide or a single electron injector structure to allow electrons to travel from the floating gate to the erase gate.

摘要翻译： 本发明涉及一种具有双层浮置栅极的单晶体管非易失性DRAM单元，以在电源中断期间允许存储电容器的内容被传送到浮动栅极。 浮动栅极的第一层通过隧道氧化物与存储电容器的存储节点分离，以允许浮置栅极和存储电容器之间的电子隧穿。 在本发明的另一个实施例中，双电子注入器结构设置在单层浮动和存储节点之间，以允许电子注入浮动栅极和存储节点之间。 在本发明的另一个实施例中，实现擦除栅极以去除浮动栅极上的电荷。 擦除栅极可以通过隧道氧化物或单个电子注入器结构与浮动栅极分离，以允许电子从浮动栅极行进到擦除栅极。

公开(公告)号：US5214603A

公开(公告)日：1993-05-25

申请号：US740758

申请日：1991-08-05

申请人： Sang H. Dhong ,  Wei Hwang ,  Lewis M. Terman ,  Matthew R. Wordeman

发明人： Sang H. Dhong ,  Wei Hwang ,  Lewis M. Terman ,  Matthew R. Wordeman

IPC分类号： H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/10 ,  H01L27/108

CPC分类号： H01L27/10832

摘要： A folded bitline DRAM cell is described which includes a trench capacitor and a planar-configured access transistor. The access transistor is stacked over the capacitor and has a first terminal connected thereto. The access transistor includes a planar-oriented gate. A first wordline has a minor surface in contact with the gate and a major surface that is oriented orthogonally to the gate. An insulating pedestal is positioned adjacent the gate and a passing wordline is positioned on the pedestal, the passing wordline having a major surface parallel to the first wordline. In another embodiment, the folded bitline DRAM cell includes a vertically oriented access transistor having one terminal formed on the upper extent of a contact to the trench capacitor, to provide optimum electrical connection thereto.

公开(公告)号：US08928350B2

公开(公告)日：2015-01-06

申请号：US13607020

申请日：2012-09-07

申请人： Liang-Teck Pang ,  Joel A. Silberman ,  Matthew R. Wordeman

发明人： Liang-Teck Pang ,  Joel A. Silberman ,  Matthew R. Wordeman

IPC分类号： H03K19/173 ,  G01R31/3185 ,  H01L25/065

CPC分类号： G01R31/318558 ,  G01R31/318513 ,  G01R31/318572 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

摘要： There is provided a strata manager within a 3D chip stack having two or more strata. The strata manager includes a plurality of scannable configuration registers, each being arranged on a respective one of the two or more strata for storing a set of bits. The set of bits is configured to program an operation of a corresponding one of the two or more strata on which the set of bits is stored or a device thereon. Additionally, a stratum identifier within a 3D stack and stack-wide scan circuit within a 3D stack are provided.

摘要翻译： 在具有两个或多个层的3D芯片堆栈中提供了层次管理器。 层管理器包括多个可扫描配置寄存器，每个配置寄存器布置在两个或更多个层中的相应一个上，用于存储一组位。 该组比特被配置为对存储有该组比特的两个或更多个层中的对应的一个或其上的装置的操作进行编程。 此外，还提供了3D堆栈内的3D堆栈和堆栈扫描电路内的层标识符。