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公开(公告)号：US10447278B1
公开(公告)日：2019-10-15
申请号：US16037587
申请日：2018-07-17
IPC分类号： H03K19/195 , H03K19/177 , G06N10/00 , G11C11/44
摘要： Superconducting logic arrays (SLAs) and field-programmable gate arrays (FPGAs) that are based on Josephson transmission lines (JTLs) accommodate reciprocal quantum logic (RQL) compliant binary input signals and provide RQL-compliant output signals that are evaluations of generalized logic functions. Each JTL-based superconducting FPGA (JTLBSFPGA) incorporates multiple JTL-based SLAs (JTLBSLAs) connected together. Each JTLBSLA includes an array of software-programmable and/or mask-programmed logic cells that output products of inputs and cell states, such that the JTLBSLAs output evaluations of sum-of-products functions. New JTLBSLA logic cells are described, including some that provide programmable cell states via magnetic Josephson junctions (MJJs). JTLBSFPGAs provide area efficiency and clock speed advantages over CMOS FPGAs. Unlike SLAs based on Josephson magnetic random access memory (JMRAM), JTLBSLAs do not require word line drivers, flux pumps, or sense amplifiers. Because JTLBSLAs and JTLBSFPGAs are RQL-compliant, they can also include RQL gates connected within or between them, without signal conversion circuitry.
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公开(公告)号：US07991955B2
公开(公告)日：2011-08-02
申请号：US11610379
申请日：2006-12-13
IPC分类号： G06F12/00
CPC分类号： G06F12/0846 , G06F12/0864
摘要： Achieving better uniformity of temperature on an integrated circuit while performing burn-in can result in reduced burn-in time and more uniform acceleration. One way to achieve better temperature uniformity is to control dynamic power in the core and cache by operating at different frequencies and increasing switching activity in the cache(s) during burn-in by changing operation of the cache so that during burn-in a plurality of memory locations in the cache(s) are accessed simultaneously, thereby increasing activity in the cache to achieve higher power utilization in the cache during burn-in.
摘要翻译： 在进行老化的同时，在集成电路上实现更好的温度均匀性可以减少老化时间和更均匀的加速。 实现更好的温度均匀性的一种方式是通过在不同频率下操作来控制核心和高速缓存中的动态功率，并且通过改变高速缓存的操作来增加在高速缓存期间的高速缓存中的切换活动，使得在老化多个 高速缓存中的存储器位置被同时访问，从而增加高速缓存中的活动以在老化期间在高速缓存中实现更高的功率利用。
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公开(公告)号：US20200028512A1
公开(公告)日：2020-01-23
申请号：US16546952
申请日：2019-08-21
IPC分类号： H03K19/195 , H03K19/177 , G06N10/00
摘要： Superconducting logic arrays (SLAs) and field-programmable gate arrays (FPGAs) that are based on Josephson transmission lines (JTLs) accommodate reciprocal quantum logic (RQL) compliant binary input signals and provide RQL-compliant output signals that are evaluations of generalized logic functions. Each JTL-based superconducting FPGA (JTLBSFPGA) incorporates multiple JTL-based SLAs (JTLBSLAs) connected together. Each JTLBSLA includes an array of software-programmable and/or mask-programmed logic cells that output products of inputs and cell states, such that the JTLBSLAs output evaluations of sum-of-products functions. New JTLBSLA logic cells are described, including some that provide programmable cell states via magnetic Josephson junctions (MJJs). JTLBSFPGAs provide area efficiency and clock speed advantages over CMOS FPGAs. Unlike SLAs based on Josephson magnetic random access memory (JMRAM), JTLBSLAs do not require word line drivers, flux pumps, or sense amplifiers. Because JTLBSLAs and JTLBSFPGAs are RQL-compliant, they can also include RQL gates connected within or between them, without signal conversion circuitry.
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公开(公告)号：US20080147976A1
公开(公告)日：2008-06-19
申请号：US11610379
申请日：2006-12-13
IPC分类号： G06F12/08
CPC分类号： G06F12/0846 , G06F12/0864
摘要： Achieving better uniformity of temperature on an integrated circuit while performing burn-in can result in reduced burn-in time and more uniform acceleration. One way to achieve better temperature uniformity is to control dynamic power in the core and cache by operating at different frequencies and increasing switching activity in the cache(s) during burn-in by changing operation of the cache so that during burn-in a plurality of memory locations in the cache(s) are accessed simultaneously, thereby increasing activity in the cache to achieve higher power utilization in the cache during burn-in.
摘要翻译： 在进行老化的同时，在集成电路上实现更好的温度均匀性可以减少老化时间和更均匀的加速。 实现更好的温度均匀性的一种方式是通过在不同频率下操作来控制核心和高速缓存中的动态功率，并且通过改变高速缓存的操作来增加在高速缓存期间的高速缓存中的切换活动，使得在老化多个 高速缓存中的存储器位置被同时访问，从而增加高速缓存中的活动以在老化期间在高速缓存中实现更高的功率利用。
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公开(公告)号：US07355881B1
公开(公告)日：2008-04-08
申请号：US11285670
申请日：2005-11-22
申请人： Floyd L. Dankert , Victor F. Andrade , Randal L. Posey , Michael K. Ciraula , Alexander W. Schaefer , Jerry D. Moench , Soolin Kao Chrudimsky , Michael C. Braganza , Jan Michael Huber , Amy M. Novak
发明人： Floyd L. Dankert , Victor F. Andrade , Randal L. Posey , Michael K. Ciraula , Alexander W. Schaefer , Jerry D. Moench , Soolin Kao Chrudimsky , Michael C. Braganza , Jan Michael Huber , Amy M. Novak
CPC分类号： G11C7/18 , G11C7/1051 , G11C7/1057 , G11C7/12 , G11C2207/002
摘要： A circuit for implementing memory arrays using a global bitline domino read/write scheme. The memory circuit includes a plurality of cells each configured to store a bit of data. The memory circuit further includes a plurality of local bitlines, wherein each cells is coupled to one of the local bitlines. Each of the plurality of local bitlines is a differential bitline having a signal path and a complementary signal path which are cross-coupled by a pair of transistors.
摘要翻译： 使用全局位线多米诺读/写方案实现存储器阵列的电路。 存储器电路包括多个单元，每个单元被配置为存储一位数据。 存储器电路还包括多个本地位线，其中每个单元耦合到本地位线之一。 多个本地位线中的每一个是具有由一对晶体管交叉耦合的信号路径和互补信号路径的差分位线。
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公开(公告)号：US07417449B1
公开(公告)日：2008-08-26
申请号：US11274595
申请日：2005-11-15
IPC分类号： G01R31/02
CPC分类号： G01R31/318511 , G01R31/31917
摘要： A system for testing integrated circuit storage structures on a semiconductor wafer. A test IC manufactured on a semiconductor wafer includes a test storage structure such as a random access memory structure, for example, and an access controller including one or more clock sources. In various embodiments, the clock sources may include a ring oscillator and a pulse width generator. These clock sources may be programmable to provide a clock signal having a variety of frequencies for accessing the storage structure. In one embodiment, the frequencies provided by the access controller may be higher than a frequency that can be supplied to the wafer from ATE. In another embodiment, the pulse width generator may be programmable to provide a pulse train having a variety of duty cycles.
摘要翻译： 一种用于在半导体晶片上测试集成电路存储结构的系统。 在半导体晶片上制造的测试IC包括例如随机存取存储器结构的测试存储结构和包括一个或多个时钟源的访问控制器。 在各种实施例中，时钟源可以包括环形振荡器和脉冲宽度发生器。 这些时钟源可以是可编程的，以提供具有用于访问存储结构的各种频率的时钟信号。 在一个实施例中，由访问控制器提供的频率可以高于可以从ATE提供给晶片的频率。 在另一个实施例中，脉冲宽度发生器可以是可编程的，以提供具有各种占空比的脉冲串。
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