-
1.发明授权Device for defeating reverse engineering of integrated circuits by optical means 失效用于通过光学方式消除集成电路逆向工程的装置公开(公告)号：US07791086B2
公开(公告)日：2010-09-07
申请号：US12610791
申请日：2009-11-02
IPC分类号： H01L27/15
CPC分类号： H01L23/576 , G01R31/311 , G01R31/31719 , H01L23/573 , H01L27/02 , H01L27/0207 , H01L2924/0002 , Y10S257/922 , H01L2924/00
摘要： An integrated circuit and method are provided for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in the integrated circuit. The method prevents, in an integrated circuit, a pattern of light emitted from at least one active device in the integrated circuit from being detected external to the integrated circuit by reduction of the intensity of light emitted from the at least one active device in the integrated circuit thereby preventing the reduced intensity light emitted from the at least one active device in the integrated circuit from being detected external to the integrated circuit. The intensity of light emitted from the at least one active device in the integrated circuit can be reduced by modification of operational characteristics of the at least one active device during switching transitions.
摘要翻译： 提供了一种用于通过监视从集成电路中的晶体管和这种电活动器件发射的光发射来防止逆向工程的集成电路和方法。 该方法在集成电路中防止从集成电路中的至少一个有源器件发射的光的图案在集成电路外部被检测，通过减少从集成电路中的至少一个有源器件发射的光的强度 从而防止在集成电路外部检测到从集成电路中的至少一个有源器件发射的强度减小的光。 可以通过在切换转换期间修改至少一个有源器件的操作特性来减小从集成电路中的至少一个有源器件发射的光的强度。
-
2.发明授权Method for defeating reverse engineering of integrated circuits by optical means 有权通过光学手段消除集成电路逆向工程的方法公开(公告)号：US07612382B2
公开(公告)日：2009-11-03
申请号：US12140714
申请日：2008-06-17
IPC分类号： H01L27/15
CPC分类号： H01L23/576 , G01R31/311 , G01R31/31719 , H01L23/573 , H01L27/02 , H01L27/0207 , H01L2924/0002 , Y10S257/922 , H01L2924/00
摘要： A method for an electronic device is provided for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in the electronic device. The method emits extraneous randomized light emissions in substantial close proximity to the transistors to hide a pattern of light emissions emitted from the transistors. As one feature, the device can include a source of randomized light emissions in substantial close proximity to the transistors to hide a pattern of the emitted light from the transistors in randomized light emissions emitted by the source. As a second feature, the device can emit the randomized light emissions by randomly delaying an electrical signal that is electrically coupled to the transistors and, in response to the randomly delayed electrical signal, the transistors randomly emitting light emissions thereby hiding a separate pattern of light emission emitted from the transistors.
摘要翻译： 提供了一种电子设备的方法，用于通过监视从电子设备中的晶体管和这种电活动设备发射的光发射来防止逆向工程。 该方法发射出与晶体管非常接近的无关随机光发射，以隐藏从晶体管发射的光发射图案。 作为一个特征，该装置可以包括基本上靠近晶体管的随机发光源，以在由源发射的随机光发射中隐藏来自晶体管的发射光的图案。 作为第二特征，设备可以通过随机延迟电耦合到晶体管的电信号来发射随机发光，并且响应于随机延迟的电信号，晶体管随机地发射光发射，从而隐藏单独的光模式 从晶体管发射的发射。
-
公开(公告)号：US06977519B2
公开(公告)日：2005-12-20
申请号：US10437764
申请日：2003-05-14
CPC分类号： H03K19/0016
摘要： A power gate structure and corresponding method are provided for controlling the ground connection of a logic circuit for a plurality of modes, where the power gate structure includes an NFET transistor, a PFET transistor in signal communication with the NFET transistor, source to source and drain to drain, respectively, a ground node in signal communication with the drains of the transistors, and a ground rail in signal communication with the sources of the transistors; and the corresponding method includes decoupling the logic circuit from the ground connection in a first or active mode, holding the logic circuit at about a threshold voltage above the ground connection in a second or state retention mode, and cutting off the current flow between the logic circuit and the ground connection in a third or non-state retentive mode.
摘要翻译： 提供了功率门结构和相应的方法，用于控制用于多个模式的逻辑电路的接地连接，其中功率栅极结构包括NFET晶体管，与NFET晶体管信号通信的PFET晶体管，源极和漏极 分别与晶体管的漏极信号通信的接地节点和与晶体管的源极信号通信的接地轨道; 并且相应的方法包括在第一或活动模式下将逻辑电路与接地连接解耦，在第二或状态保持模式下将逻辑电路保持在接地连接以上的阈值电压处，并且切断逻辑电流之间的电流 电路和接地连接处于第三或非状态保持模式。
-
4.发明授权Method and apparatus for reverse engineering integrated circuits by monitoring optical emission 有权通过监控光发射逆向工程集成电路的方法和装置公开(公告)号：US06496022B1
公开(公告)日：2002-12-17
申请号：US09468999
申请日：1999-12-21
IPC分类号： G01R31302
CPC分类号： G01R31/311 , G01R31/2894
摘要： A method and apparatus for reverse engineering an integrated circuit chip (IC chip) (120) utilizes an electrical circuit tester (114) for injecting a triggering signal into the IC chip (120) to exercise a circuit under test. In synchronization thereto, a PICA detector (116) monitors optical emissions from the circuit under test. A spatial data extractor, electrically coupled to the PICA detector, collects space information (124) from patterns of light emissions emitted by the circuit under test, and a timing data extractor, electrically coupled to the electrical circuit tester and to the PICA detector (116), collects time information (126) from the patterns of light emissions emitted by the circuit under test. A database memory (105) includes known data about the circuit under test and also includes at least one reference pattern for comparing a captured light emission pattern thereto to identify at least one circuit element in the circuit under test. A PICA data analyzer (108), electrically coupled to the database memory (105) and to the PICA detector (116), determines at least one of whether the circuit under test comprises a circuit element with a light emission pattern that matches one of the at least one reference pattern in the database memory (105), and the value contained in a memory in the IC chip (120).
摘要翻译： 用于逆向工程的集成电路芯片（IC芯片）（120）的方法和装置利用电路测试器（114）将触发信号注入到IC芯片（120）中以锻炼被测电路。 与此同步，PICA检测器（116）监测来自被测电路的光发射。 电耦合到PICA检测器的空间数据提取器从由被测电路发射的光发射模式收集空间信息（124）和电耦合到电路测试器和PICA检测器（116）的定时数据提取器 ）从所测试的电路发出的光发射模式收集时间信息（126）。 数据库存储器（105）包括关于被测电路的已知数据，并且还包括至少一个用于将捕获的发光图案与其进行比较的参考图案，以识别被测电路中的至少一个电路元件。 电耦合到数据库存储器（105）和PICA检测器（116）的PICA数据分析器（108）确定被测电路中是否包含具有与发光模式匹配的发光模式的电路元件中的至少一个 数据库存储器（105）中的至少一个参考图案，以及包含在IC芯片（120）中的存储器中的值。
-
5.发明授权Device for defeating reverse engineering of integrated circuits by optical means 失效用于通过光学方式消除集成电路逆向工程的装置公开(公告)号：US07791087B2
公开(公告)日：2010-09-07
申请号：US12610808
申请日：2009-11-02
IPC分类号： H01L27/15
CPC分类号： H01L23/576 , G01R31/311 , G01R31/31719 , H01L23/573 , H01L27/02 , H01L27/0207 , H01L2924/0002 , Y10S257/922 , H01L2924/00
摘要： An integrated circuit and method are provided for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in the integrated circuit. The method prevents, in an integrated circuit, a pattern of light emitted from at least one active device in the integrated circuit from being detected external to the integrated circuit by fading the light emitted from the at least one active device in the integrated circuit and that is emitted external to the integrated circuit. Bright light emission emitted in substantial close proximity to the at least one active device in the integrated circuit, and emitted external to the integrated circuit, fades a pattern of light emission emitted from the at least one active device.
摘要翻译： 提供了一种用于通过监视从集成电路中的晶体管和这种电活动器件发射的光发射来防止逆向工程的集成电路和方法。 该方法在集成电路中防止从集成电路中的至少一个有源器件发射的光的图案通过使从集成电路中的至少一个有源器件发射的光衰减而在集成电路外部被检测到在集成电路外部被检测，并且以及从集成电路中的至少一个有源器件发出的光的衰减，以及 在集成电路外部发射。 在集成电路中实质上非常接近于至少一个有源器件发射并且被发射到集成电路外部的明亮的发光使得从至少一个有源器件发射的发光模式变淡。
-
6.发明申请DEVICE FOR DEFEATING REVERSE ENGINEERING OF INTEGRATED CIRCUITS BY OPTICAL MEANS 失效通过光学手段防止集成电路反向工程的设备公开(公告)号：US20100044725A1
公开(公告)日：2010-02-25
申请号：US12610808
申请日：2009-11-02
IPC分类号： H01L27/15
CPC分类号： H01L23/576 , G01R31/311 , G01R31/31719 , H01L23/573 , H01L27/02 , H01L27/0207 , H01L2924/0002 , Y10S257/922 , H01L2924/00
摘要： An integrated circuit and method are provided for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in the integrated circuit. The method prevents, in an integrated circuit, a pattern of light emitted from at least one active device in the integrated circuit from being detected external to the integrated circuit by fading the light emitted from the at least one active device in the integrated circuit and that is emitted external to the integrated circuit. Bright light emission emitted in substantial close proximity to the at least one active device in the integrated circuit, and emitted external to the integrated circuit, fades a pattern of light emission emitted from the at least one active device.
摘要翻译： 提供了一种用于通过监视从集成电路中的晶体管和这种电活动器件发射的光发射来防止逆向工程的集成电路和方法。 该方法在集成电路中防止从集成电路中的至少一个有源器件发射的光的图案通过使从集成电路中的至少一个有源器件发射的光衰减而在集成电路外部被检测到在集成电路外部被检测，并且以及从集成电路中的至少一个有源器件发出的光 在集成电路外部发射。 在集成电路中实质上非常接近于至少一个有源器件发射并且被发射到集成电路外部的明亮的发光使得从至少一个有源器件发射的发光模式变淡。
-
7.发明申请Register file cell with soft error detection and circuits and methods using the cell 失效使用软件错误检测注册文件单元，使用单元格的电路和方法公开(公告)号：US20070300131A1
公开(公告)日：2007-12-27
申请号：US11446348
申请日：2006-06-02
IPC分类号： G11C29/00
CPC分类号： G11C29/52 , G11C29/32 , G11C2029/3202
摘要： Techniques are provided for a register file cell that includes a primary storage portion configured to store a first value, and a secondary storage portion that is coupled to the primary storage portion. The secondary storage portion is configured to function as a scan latch during a test operation, and is further configured to store a second value during normal operation. The second value is a duplicate of the first value. The cell further includes an error detection portion that is coupled to the primary storage portion and the secondary storage portion and is configured to indicate a difference between the first value and the second value, caused by a soft error.
摘要翻译： 为包括被配置为存储第一值的主存储部分和耦合到主存储部分的辅助存储部分的寄存器文件单元提供技术。 次存储部分被配置为在测试操作期间用作扫描锁存器，并且还被配置为在正常操作期间存储第二值。 第二个值是第一个值的副本。 小区还包括错误检测部分，其耦合到主存储部分和辅助存储部分，并且被配置为指示由软错误引起的第一值和第二值之间的差异。
-
8.发明授权Device for defeating reverse engineering of integrated circuits by optical means 失效用于通过光学方式消除集成电路逆向工程的装置公开(公告)号：US06515304B1
公开(公告)日：2003-02-04
申请号：US09603570
申请日：2000-06-23
IPC分类号： H01L3300
CPC分类号： H01L23/576 , G01R31/311 , G01R31/31719 , H01L23/573 , H01L27/02 , H01L27/0207 , H01L2924/0002 , Y10S257/922 , H01L2924/00
摘要： An integrated circuit chip (IC) is equipped with a device for preventing reverse engineering by monitoring light emissions emitted from transistors and such electrically active devices in a circuit located in the IC. The device can be an opaque structure that blocks emissions from being detected external to the IC. Alternatively, the device can reduce light emissions from the transistors to prevent detection of the light emissions external to the IC. The device, in another alternative, can emit extraneous light emissions to hide a pattern of light emissions emitted from the transistors. As a further alternative, the device can add random delay to a signal driving the transistors to randomize the pattern of light emissions emitted from the transistors to prevent detection of a predetermined pattern of light emissions external to the IC.
摘要翻译： 集成电路芯片（IC）配备有通过监视位于IC中的电路中的晶体管和这种电活动器件发射的发光来防止逆向工程的装置。 该器件可以是阻挡在IC外部检测到发射的不透明结构。 或者，该器件可以减少来自晶体管的光发射，以防止IC外部的光发射的检测。 在另一个替代方案中，该装置可以发射外部光发射以隐藏从晶体管发射的光发射模式。 作为另外的替代方案，器件可以向驱动晶体管的信号增加随机延迟，以随机化从晶体管发射的发光模式，以防止检测IC外部的预定的光发射模式。
-
9.发明授权Register file cell with soft error detection and circuits and methods using the cell 失效使用软件错误检测注册文件单元，使用单元格的电路和方法公开(公告)号：US07562273B2
公开(公告)日：2009-07-14
申请号：US11446348
申请日：2006-06-02
IPC分类号： G01R31/28
CPC分类号： G11C29/52 , G11C29/32 , G11C2029/3202
摘要： Techniques are provided for a register file cell that includes a primary storage portion configured to store a first value, and a secondary storage portion that is coupled to the primary storage portion. The secondary storage portion is configured to function as a scan latch during a test operation, and is further configured to store a second value during normal operation. The second value is a duplicate of the first value. The cell further includes an error detection portion that is coupled to the primary storage portion and the secondary storage portion and is configured to indicate a difference between the first value and the second value, caused by a soft error.
摘要翻译： 为包括被配置为存储第一值的主存储部分和耦合到主存储部分的辅助存储部分的寄存器文件单元提供技术。 次存储部分被配置为在测试操作期间用作扫描锁存器，并且还被配置为在正常操作期间存储第二值。 第二个值是第一个值的副本。 小区还包括错误检测部分，其耦合到主存储部分和辅助存储部分，并且被配置为指示由软错误引起的第一值和第二值之间的差异。
-
公开(公告)号：US07486108B2
公开(公告)日：2009-02-03
申请号：US11518078
申请日：2006-09-08
IPC分类号： H03K17/16
CPC分类号： H03K19/0019
摘要： A charge recycling power gate and corresponding method are provided for using a charge sharing effect between a capacitive load of a functional unit and a parasitic capacitance of a charge recycling means to turn on a switching means between a virtual ground and a ground, the charge recycling power gate including a first transistor, a virtual ground in signal communication with a first terminal of the first transistor, a ground in signal communication with a second terminal of the first transistor, a capacitor having a first terminal in signal communication with a third terminal of the first transistor and a second terminal in signal communication with the ground, and a second transistor having a first terminal in signal communication with the virtual ground and a second terminal in signal communication with the third terminal of the first transistor.
摘要翻译： 提供电荷回收功率门和相应的方法，用于使用功能单元的电容性负载与电荷回收装置的寄生电容之间的电荷共享效应，以接通虚拟地面和地面之间的开关装置，电荷回收 功率门，包括第一晶体管，与第一晶体管的第一端子进行信号通信的虚拟地，与第一晶体管的第二端子进行信号通信的地，电容器，具有与第三晶体管的第三端子信号通信的第一端子 第一晶体管和与地面信号通信的第二端子，以及第二晶体管，其具有与虚拟接地信号通信的第一端子和与第一晶体管的第三端子信号通信的第二端子。
-
-
-
-
-
-
-
-
-
搜索结果
26 条记录 (耗时 0.017 秒)
