公开(公告)号：US08994085B2

公开(公告)日：2015-03-31

申请号：US13551714

申请日：2012-07-18

Applicant: Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tenko Yamashita ,  Chun-Chen Yeh

Inventor： Veeraraghavan S. Basker ,  Kangguo Cheng ,  Bruce B. Doris ,  Terence B. Hook ,  Ali Khakifirooz ,  Pranita Kulkarni ,  Tenko Yamashita ,  Chun-Chen Yeh

IPC: H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119 ,  H01L21/84 ,  H01L27/11 ,  H01L27/12

CPC classification number: H01L21/84 ,  H01L27/10861 ,  H01L27/1087 ,  H01L27/10873 ,  H01L27/10894 ,  H01L27/10897 ,  H01L27/1108 ,  H01L27/1116 ,  H01L27/1203 ,  H01L29/945

Abstract: An integrated circuit comprising an N+ type layer, a buffer layer arranged on the N+ type layer; a P type region formed on with the buffer layer; an insulator layer overlying the N+ type layer, a silicon layer overlying the insulator layer, an embedded RAM FET formed in the silicon layer and connected with a conductive node of a trench capacitor that extends into the N+ type layer, the N+ type layer forming a plate electrode of the trench capacitor, a first contact through the silicon layer and the insulating layer and electrically connecting to the N+ type layer, a first logic RAM FET formed in the silicon layer above the P type region, the P type region functional as a P-type back gate of the first logic RAM FET, and a second contact through the silicon layer and the insulating layer and electrically connecting to the P type region.

Abstract translation: 一种集成电路，包括N +型层，设置在N +型层上的缓冲层; 形成在缓冲层上的P型区域; 覆盖N +型层的绝缘体层，覆盖绝缘体层的硅层，形成在硅层中并与延伸到N +型层的沟槽电容器的导电节点连接的嵌入式RAM FET，N +型层形成 沟槽电容器的平板电极，通过硅层和绝缘层的第一接触并且电连接到N +型层，形成在P型区域上方的硅层中的第一逻辑RAM FET，P型区域用作 第一逻辑RAM FET的P型背栅，以及通过硅层和绝缘层的第二接触，并且电连接到P型区域。

公开(公告)号：US08716797B2

公开(公告)日：2014-05-06

申请号：US12611444

申请日：2009-11-03

Applicant: Veeraraghavan S. Basker ,  Chang Kangguo ,  Bruce B. Doris ,  Johnathan E. Faltermeier

Inventor： Veeraraghavan S. Basker ,  Chang Kangguo ,  Bruce B. Doris ,  Johnathan E. Faltermeier

IPC: H01L27/12

CPC classification number: H01L29/66795 ,  H01L21/26586 ,  H01L21/823431 ,  H01L29/66803 ,  H01L29/785

Abstract: A FinFET having spacers with a substantially uniform profile along the length of a gate stack which covers a portion of a fin of semiconductor material formed on a substrate is provided by depositing spacer material conformally on both the fins and gate stack and performing an angled ion impurity implant approximately parallel to the gate stack to selectively cause damage to only spacer material deposited on the fin. Due to the damage caused by the angled implant, the spacer material on the fins can be etched with high selectivity to the spacer material on the gate stack.

Abstract translation: 通过在翅片和栅极堆叠上共同沉积间隔材料并执行成角度的离子杂质来提供具有覆盖形成在衬底上的半导体材料的翅片的一部分的栅极叠层长度上具有基本上均匀分布的间隔物的FinFET 大致平行于栅极堆叠的植入物选择性地仅对沉积在鳍片上的间隔物材料造成损害。 由于由成角度的植入物引起的损伤，翅片上的间隔物材料可以以高选择性蚀刻到栅极堆叠上的间隔物材料。

公开(公告)号：US08703572B2

公开(公告)日：2014-04-22

申请号：US13269955

申请日：2011-10-10

Applicant: Veeraraghavan S. Basker ,  Richard Q. Williams

Inventor： Veeraraghavan S. Basker ,  Richard Q. Williams

IPC: H01L21/331

CPC classification number: H01L28/60 ,  H01L27/108 ,  H01L27/10861 ,  H01L28/91 ,  H01L29/66181 ,  H01L29/945

Abstract: A method and structure is directed to eDRAM cells with high-conductance electrodes. The method includes forming upper layers on a semiconductor substrate and forming an opening in the upper layers. The method further includes forming a trench in the semiconductor substrate, aligned with the opening. The method further includes forming a metal plate on all exposed surface in the trench by applying a metallic aqueous solution with an electrical bias to a backside of the semiconductor substrate.

Abstract translation: 方法和结构针对具有高电导电极的eDRAM细胞。 该方法包括在半导体衬底上形成上层并在上层形成开口。 该方法还包括在半导体衬底中形成与开口对准的沟槽。 该方法还包括通过将具有电偏压的金属水溶液施加到半导体衬底的背面而在沟槽的所有暴露表面上形成金属板。

公开(公告)号：US20140030864A1

公开(公告)日：2014-01-30

申请号：US13556437

申请日：2012-07-24

Applicant: Veeraraghavan S. BASKER ,  Sivananda KANAKASABAPATHY ,  Tenko YAMASHITA ,  Chun-Chen YEH

Inventor： Veeraraghavan S. BASKER ,  Sivananda KANAKASABAPATHY ,  Tenko YAMASHITA ,  Chun-Chen YEH

IPC: H01L21/02

CPC classification number: H01L27/10867 ,  H01L21/845 ,  H01L27/10826 ,  H01L27/1087 ,  H01L27/10879 ,  H01L27/1211

Abstract: The specification and drawings present a new method, device and computer/software related product (e.g., a computer readable memory) are presented for realizing eDRAM strap formation in Fin FET device structures. Semiconductor on insulator (SOI) substrate comprising at least an insulator layer between a first semiconductor layer and a second semiconductor layer is provided. The (metal) strap formation is accomplished by depositing conductive layer on fins portion of the second semiconductor layer (Si) and a semiconductor material (polysilicon) in each DT capacitor extending to the second semiconductor layer. The metal strap is sealed by a nitride spacer to prevent the shorts between PWL and DT capacitors.

Abstract translation: 说明书和附图提出了一种新的方法，设备和计算机/软件相关产品（例如，计算机可读存储器），用于实现Fin FET器件结构中的eDRAM带形成。 提供了在第一半导体层和第二半导体层之间至少包括绝缘体层的半导体绝缘体（SOI）衬底。 （金属）带形成是通过在第二半导体层（Si）的鳍部分上沉积导电层和延伸到第二半导体层的每个DT电容器中的半导体材料（多晶硅）来实现的。 金属带由氮化物间隔物密封，以防止PWL和DT电容器之间的短路。

公开(公告)号：US20130313649A1

公开(公告)日：2013-11-28

申请号：US13524131

申请日：2012-06-15

Applicant: VEERARAGHAVAN S. BASKER ,  EFFENDI LEOBANDUNG ,  TENKO YAMASHITA ,  CHUN-CHEN YEH

Inventor： VEERARAGHAVAN S. BASKER ,  EFFENDI LEOBANDUNG ,  TENKO YAMASHITA ,  CHUN-CHEN YEH

IPC: H01L27/088

CPC classification number: H01L21/845 ,  H01L27/1211

Abstract: Multigate transistor devices and methods of their fabrication are disclosed. One such device includes a plurality of semiconductor fins that have source and drain regions and a gate structure overlaying the fins. The device further includes a dielectric layer that is beneath the gate structure and the fins. Here, the dielectric layer includes first dielectric regions that are disposed beneath the fins and second dielectric regions that are disposed between the fins. In addition, the first dielectric regions have a density that is greater than a density of the second dielectric regions.

Abstract translation: 公开了多晶体管器件及其制造方法。 一种这样的装置包括具有源极和漏极区域以及覆盖鳍片的栅极结构的多个半导体鳍片。 该器件还包括在栅极结构和鳍片之下的介电层。 这里，电介质层包括设置在散热片之下的第一介电区域和设置在散热片之间的第二电介质区域。 此外，第一电介质区域的密度大于第二电介质区域的密度。

公开(公告)号：US08455313B1

公开(公告)日：2013-06-04

申请号：US13617709

申请日：2012-09-14

Applicant: Veeraraghavan S. Basker ,  Andres Bryant ,  Huiming Bu ,  Wilfried Haensch ,  Effendi Leobandung ,  Chung-Hsun Lin ,  Theodorus E. Standaert ,  Tenko Yamashita ,  Chun-chen Yeh

Inventor： Veeraraghavan S. Basker ,  Andres Bryant ,  Huiming Bu ,  Wilfried Haensch ,  Effendi Leobandung ,  Chung-Hsun Lin ,  Theodorus E. Standaert ,  Tenko Yamashita ,  Chun-chen Yeh

IPC: H01L21/336

CPC classification number: H01L29/41791 ,  H01L29/66795

Abstract: A method is provided for fabricating a finFET device. Fin structures are formed over a BOX layer. The fin structures include a semiconductor layer and extend in a first direction. A gate stack is formed on the BOX layer over the fin structures and extending in a second direction. The gate stack includes a high-K dielectric layer and a metal gate. Gate spacers are formed on sidewalls of the gate stack, and an epi layer is deposited to merge the fin structures. Ions are implanted to form source and drain regions, and dummy spacers are formed on sidewalls of the gate spacers. The dummy spacers are used as a mask to recess or completely remove an exposed portion of the epi layer. Silicidation forms silicide regions that abut the source and drain regions and each include a vertical portion located on the vertical sidewall of the source or drain region.

Abstract translation: 提供了一种用于制造finFET器件的方法。 翅片结构形成在BOX层上。 翅片结构包括半导体层并沿第一方向延伸。 栅极叠层形成在鳍状结构上的BOX层上并沿第二方向延伸。 栅极堆叠包括高K电介质层和金属栅极。 栅极间隔物形成在栅极堆叠的侧壁上，并且沉积外延层以使翅片结构合并。 植入离子以形成源极和漏极区，并且在栅极间隔物的侧壁上形成虚设间隔物。 虚拟间隔物用作掩模以凹进或完全去除外延层的暴露部分。 硅化形成邻接源极和漏极区域的硅化物区域，并且每个都包括位于源极或漏极区域的垂直侧壁上的垂直部分。

公开(公告)号：US20120322243A1

公开(公告)日：2012-12-20

申请号：US13596593

申请日：2012-08-28

Applicant: Veeraraghavan S. Basker ,  John M. Cotte ,  Hariklia Deligianni ,  Matteo Flotta

Inventor： Veeraraghavan S. Basker ,  John M. Cotte ,  Hariklia Deligianni ,  Matteo Flotta

IPC: H01L21/326

CPC classification number: C25D5/54 ,  C25D5/006 ,  C25D5/02 ,  C25D7/123 ,  C25D11/005 ,  C25D11/024 ,  C25D17/001 ,  C25F3/14 ,  H01L21/28079 ,  H01L21/2885

Abstract: An electrochemical process comprising: providing a 125 mm or larger semiconductor wafer in electrical contact with a conducting surface, wherein at least a portion of the semiconductor wafer is in contact with an electrolytic solution, said semiconductor wafer functioning as a first electrode; providing a second electrode in the electrolytic solution, the first and second electrode connected to opposite ends of an electric power source; and irradiating a surface of the semiconductor wafer with a light source as an electric current is applied across the first and the second electrodes. The invention is also directed to an apparatus including a light source and electrochemical components to conduct the electrochemical process.

公开(公告)号：US20120318666A1

公开(公告)日：2012-12-20

申请号：US13561599

申请日：2012-07-30

Applicant: Veeraraghavan S. Basker ,  Eduard Cartier ,  Hariklia Deligianni ,  Rajarao Jammy ,  Vamsi K. Paruchuri

Inventor： Veeraraghavan S. Basker ,  Eduard Cartier ,  Hariklia Deligianni ,  Rajarao Jammy ,  Vamsi K. Paruchuri

IPC: C25D19/00

CPC classification number: C25D5/18 ,  C25D5/024 ,  C25D17/001 ,  C25D17/002 ,  C25D17/005 ,  H01L21/2885 ,  H01L21/7624

Abstract: An electroplating apparatus and method for depositing a metallic layer on the surface of a wafer is provided wherein said apparatus and method do not require physical attachment of an electrode to the wafer. The surface of the wafer to be plated is positioned to face the anode and a plating fluid is provided between the wafer and the electrodes to create localized metallic plating. The wafer may be positioned to physically separate and lie between the anode and cathode so that one side of the wafer facing the anode contains a catholyte solution and the other side of the wafer facing the cathode contains an anolyte solution. Alternatively, the anode and cathode may exist on the same side of the wafer in the same plating fluid. In one example, the anode and cathode are separated by a semi permeable membrane.

Abstract translation: 提供了一种用于在晶片的表面上沉积金属层的电镀设备和方法，其中所述设备和方法不需要将电极物理附接到晶片。 要镀覆的晶片的表面被定位成面对阳极，并且在晶片和电极之间设置电镀液以产生局部金属电镀。 晶片可以被定位成物理分离并且位于阳极和阴极之间，使得面向阳极的晶片的一侧包含阴极电解液，并且晶片的面向阴极的另一侧包含阳极电解液。 或者，阳极和阴极可以存在于同一电镀液中晶片的同一侧。 在一个实例中，阳极和阴极被半透膜隔开。

公开(公告)号：US08299605B2

公开(公告)日：2012-10-30

申请号：US11939599

申请日：2007-11-14

Applicant: Veeraraghavan S Basker ,  Toshiharu Furukawa ,  Mark C Hakey ,  Steven J Holmes ,  Charles W Koburger, III ,  Krishna V Singh

Inventor： Veeraraghavan S Basker ,  Toshiharu Furukawa ,  Mark C Hakey ,  Steven J Holmes ,  Charles W Koburger, III ,  Krishna V Singh

IPC: H01L23/34

CPC classification number: H01L23/373 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/6835 ,  H01L23/3157 ,  H01L23/433 ,  H01L24/11 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/27 ,  H01L24/81 ,  H01L24/94 ,  H01L29/0657 ,  H01L2221/6835 ,  H01L2221/68377 ,  H01L2224/0401 ,  H01L2224/05026 ,  H01L2224/05186 ,  H01L2224/05561 ,  H01L2224/05564 ,  H01L2224/05571 ,  H01L2224/05655 ,  H01L2224/05657 ,  H01L2224/0566 ,  H01L2224/10135 ,  H01L2224/113 ,  H01L2224/11845 ,  H01L2224/13021 ,  H01L2224/13076 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13184 ,  H01L2224/13187 ,  H01L2224/13193 ,  H01L2224/16221 ,  H01L2224/1703 ,  H01L2224/17515 ,  H01L2224/274 ,  H01L2224/73253 ,  H01L2224/81139 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81493 ,  H01L2924/00014 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/04953 ,  H01L2224/05552

Abstract: Disclosed are embodiments of an improved semiconductor wafer structure having protected clusters of carbon nanotubes (CNTs) on the back surface and a method of forming the improved semiconductor wafer structure. Also disclosed are embodiments of a semiconductor module with exposed CNTs on the back surface for providing enhanced thermal dissipation in conjunction with a heat sink and a method of forming the semiconductor module using the disclosed semiconductor wafer structure.

Abstract translation: 公开了在后表面上具有碳纳米管（CNT）的保护簇的改进的半导体晶片结构的实施方案和形成改进的半导体晶片结构的方法。 还公开了在后表面上具有暴露的CNT的半导体模块的实施例，用于与散热器一起提供增强的散热以及使用所公开的半导体晶片结构形成半导体模块的方法。

公开(公告)号：US20120181613A1

公开(公告)日：2012-07-19

申请号：US13009271

申请日：2011-01-19

Applicant: Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  Steven J. Holmes ,  Sivananda K. Kanakasabapathy

Inventor： Veeraraghavan S. Basker ,  Toshiharu Furukawa ,  Steven J. Holmes ,  Sivananda K. Kanakasabapathy

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/8238

CPC classification number: H01L29/66477 ,  H01L21/823418 ,  H01L21/823468 ,  H01L29/78

Abstract: A method for forming a field effect transistor device includes forming a first gate stack and a second gate stack on a substrate, depositing a first photoresist material over the second gate stack and a portion of the substrate, implanting ions in exposed regions of the substrate to define a first source region and a first drain region adjacent to the first gate stack, depositing a first protective layer over the first source region, the first gate stack, the first drain region, and the first photoresist material, removing portions of the first protective layer to expose the first photoresist material and to define a first spacer disposed on a portion of the first source region and a portion of the first drain region, removing the first photoresist material, and removing the first spacer.

Abstract translation: 一种用于形成场效应晶体管器件的方法包括在衬底上形成第一栅极堆叠和第二栅极叠层，在第二栅极堆叠上沉积第一光致抗蚀剂材料和衬底的一部分，将衬底的暴露区域中的离子注入到 限定与第一栅极堆叠相邻的第一源极区域和第一漏极区域，在第一源极区域，第一栅极堆叠层，第一漏极区域和第一光致抗蚀剂材料上沉积第一保护层，去除第一保护层 以露出第一光致抗蚀剂材料并且限定设置在第一源极区域和第一漏极区域的一部分上的第一间隔物，去除第一光致抗蚀剂材料，以及移除第一间隔物。