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1.
公开(公告)号:US10284176B1
公开(公告)日:2019-05-07
申请号:US14730001
申请日:2015-06-03
发明人: Marc Solal
摘要: Embodiments described herein may provide a surface acoustic wave (SAW) device, methods of fabricating the SAW device, and a system incorporating the SAW device. The SAW device may include a piezoelectric substrate and individual resonators may be formed by a plurality of electrodes on the surface of the piezoelectric substrate. A dielectric layer having a positive thermal coefficient of frequency (TCF) may be formed on each of the plurality of electrodes. In various embodiments, temperature compensation may be achieved by providing more or less of the dielectric layer on at least one resonator than on the other resonators based on a configuration of the resonators. In various embodiments, temperature compensation may be achieved by providing at least one resonator with a different duty factor than the other resonators based on a configuration of the resonators.
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公开(公告)号:US20190013791A1
公开(公告)日:2019-01-10
申请号:US16130433
申请日:2018-09-13
发明人: Shogo Inoue , Marc Solal
摘要: Embodiments of a Surface Acoustic Wave (SAW) device having a guided SAW structure that provides spurious mode suppression and methods of fabrication thereof are disclosed. In some embodiments, a SAW device includes a non-semiconductor support substrate, a piezoelectric layer on a surface of the non-semiconductor support substrate, and at least one interdigitated transducer on a surface of the piezoelectric layer opposite the non-semiconductor support substrate. A thickness of the piezoelectric layer, a SAW velocity of the piezoelectric layer, and an acoustic velocity of the non-semiconductor support substrate are such that a frequency of spurious modes above a resonance frequency of the SAW device is above a bulk wave cut-off frequency of the SAW device. In this manner, the spurious modes above the resonance frequency of the SAW device are suppressed.
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公开(公告)号:US10109623B2
公开(公告)日:2018-10-23
申请号:US15142404
申请日:2016-04-29
摘要: A semiconductor device includes a first varactor diode and a second varactor diode. The second varactor diode is coupled in series with the first varactor diode and vertically disposed over the first varactor diode. By vertically disposing the second varactor diode over the first varactor diode, the space occupied by the pair of varactor diodes can be significantly reduced.
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公开(公告)号:US09985194B1
公开(公告)日:2018-05-29
申请号:US14711679
申请日:2015-05-13
发明人: Alireza Tajic
IPC分类号: H03H9/17 , H01L41/047
CPC分类号: H01L41/0477
摘要: Embodiments provide a solidly-mounted bulk acoustic wave (BAW) resonator and method of making same. In embodiments, the BAW resonator may include a planzarization portion in an inactive region of the BAW resonator that is coplanar with a piezoelectric layer of the BAW resonator in an active region of the BAW restonator. Other embodiments may be described and claimed.
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公开(公告)号:US09780740B2
公开(公告)日:2017-10-03
申请号:US14153935
申请日:2014-01-13
CPC分类号: H03F3/195 , H03F1/3247 , H03F3/24 , H03F2200/411 , H04B1/0475 , H04B1/18 , H04B2001/0408
摘要: Embodiments of the present disclosure describe apparatuses, methods, and systems of front end module (FEM) having a feedback path that includes a passive attenuation network. The passive attenuation network may provide a feedback signal to a receive output port of the FEM that may be used as a basis for predistortion. Other embodiments may also be described and/or claimed.
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公开(公告)号:US20170222618A1
公开(公告)日:2017-08-03
申请号:US15086936
申请日:2016-03-31
发明人: Shogo Inoue , Marc Solal
CPC分类号: H03H9/02818 , H03H9/02543 , H03H9/02574 , H03H9/02787 , H03H9/131 , H03H9/14564 , H03H9/6406
摘要: Embodiments of a Surface Acoustic Wave (SAW) device having a guided SAW structure that provides spurious mode suppression and methods of fabrication thereof are disclosed. In some embodiments, a SAW device includes a non-semiconductor support substrate, a piezoelectric layer on a surface of the non-semiconductor support substrate, and at least one interdigitated transducer on a surface of the piezoelectric layer opposite the non-semiconductor support substrate. A thickness of the piezoelectric layer, a SAW velocity of the piezoelectric layer, and an acoustic velocity of the non-semiconductor support substrate are such that a frequency of spurious modes above a resonance frequency of the SAW device is above a bulk wave cut-off frequency of the SAW device. In this manner, the spurious modes above the resonance frequency of the SAW device are suppressed.
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7.
公开(公告)号:US20170110434A1
公开(公告)日:2017-04-20
申请号:US15085458
申请日:2016-03-30
IPC分类号: H01L23/00
CPC分类号: H01L24/81 , H01L21/56 , H01L23/3164 , H01L23/3185 , H01L24/09 , H01L24/17 , H01L2224/0901 , H01L2224/0912 , H01L2224/13005 , H01L2224/131 , H01L2224/13564 , H01L2224/13566 , H01L2224/1369 , H01L2224/16227 , H01L2224/1705 , H01L2224/17106 , H01L2224/81191 , H01L2224/812 , H01L2224/8121 , H01L2224/81355 , H01L2224/81375 , H01L2224/81385 , H01L2224/81395 , H01L2224/81815 , H01L2224/81862 , H01L2224/81905 , H01L2924/3512 , H01L2924/00014 , H01L2224/81904 , H01L2924/206 , H01L2924/014
摘要: The present disclosure relates to a flip-chip package with a hollow-cavity and reinforced interconnects, and a process for making the same. The disclosed flip-chip package includes a substrate, a reinforcement layer over an upper surface of the substrate, a flip-chip die attached to the upper surface of the substrate by interconnects through the reinforcement layer, an air cavity formed between the substrate and the flip-chip die, and a protective layer encapsulating the flip-chip die and defining a perimeter of the air cavity. Herein, a first portion of each interconnect is encapsulated by the reinforcement layer and a second portion of each interconnect is exposed to the air cavity. The reinforcement layer provides reinforcement to each interconnect.
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公开(公告)号:US09484471B2
公开(公告)日:2016-11-01
申请号:US14485532
申请日:2014-09-12
发明人: Peter V. Wright
IPC分类号: H01L29/93 , H01L29/66 , H01L29/861 , H01L27/08
CPC分类号: H01L29/66174 , H01L27/0808 , H01L29/6609 , H01L29/66121 , H01L29/66128 , H01L29/861 , H01L29/93
摘要: Embodiments include apparatuses and methods related to a compound varactor. A first varactor in the compound varactor may include a collector layer and a first base layer that is arranged in a first plurality of parallel fingers. A second varactor in the compound varactor may include a second base layer arranged in a second plurality of parallel fingers, and the base layer may be coupled with the collector layer. In embodiments, the fingers of the base layers of the first varactor and the second varactor may be interleaved with one another. Other embodiments may be disclosed or claimed herein.
摘要翻译: 实施例包括与复合变容二极管相关的装置和方法。 复合变量反应器中的第一变容二极管可以包括集电极层和布置在第一多个平行指状物中的第一基极层。 复合变量反应器中的第二变容二极管可以包括布置在第二多个平行指中的第二基极层,并且基极层可以与集电极层耦合。 在实施例中,第一变容二极管和第二变容二极管的基极层的指状物可彼此交错。 本文中可以公开或要求其他实施例。
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公开(公告)号:US20160240511A1
公开(公告)日:2016-08-18
申请号:US15140928
申请日:2016-04-28
发明人: Robert Charles Dry , Steve Jones , Jonathan Fain
IPC分类号: H01L25/065 , H01L23/367 , H01L23/047 , H01L23/00 , H01L23/498 , H01L23/08 , H01L23/057
CPC分类号: H01L25/0655 , H01L23/047 , H01L23/10 , H01L23/13 , H01L23/36 , H01L23/5383 , H01L24/32 , H01L24/48 , H01L24/49 , H01L24/73 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48137 , H01L2224/48177 , H01L2224/49111 , H01L2224/49175 , H01L2224/73265 , H01L2224/83447 , H01L2224/83805 , H01L2924/00014 , H01L2924/01047 , H01L2924/01079 , H01L2924/15153 , H01L2924/15724 , H01L2924/15738 , H01L2924/15747 , H01L2924/16152 , H01L2224/45099 , H01L2224/45015 , H01L2924/207 , H01L2224/05599
摘要: The present disclosure relates to a ring-frame power package. In this regard, the ring-frame power package includes a thermal carrier and a ring structure. The thermal carrier has a carrier surface. The ring structure includes a ring body that is disposed over the carrier surface of the thermal carrier so that a portion of the carrier surface is exposed through an interior opening of the ring body. The ring-frame power package also includes a power package lid that is disposed over the ring body. The power package lid includes a cavity in communication with the interior opening of the ring body. In this manner, the power package lid covers and protects semiconductor devices and corresponding wires encased by the ring-frame power package.
摘要翻译: 本发明涉及一种环形电源封装。 在这方面,环形框架功率封装包括热载体和环形结构。 热载体具有载体表面。 环形结构包括设置在热载体的载体表面上的环体,使得载体表面的一部分通过环体的内部开口露出。 环形框架功率封装还包括设置在环体上的电源封装盖。 功率封装盖包括与环体的内部开口连通的空腔。 以这种方式,功率封装盖覆盖并保护半导体器件和由环形框架功率封装件包围的对应的电线。
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公开(公告)号:US09379698B2
公开(公告)日:2016-06-28
申请号:US14172727
申请日:2014-02-04
发明人: George Nohra
IPC分类号: H03K17/30 , H03K17/16 , H03K17/687
CPC分类号: H03K17/162 , H03K17/165 , H03K17/6872 , H03K17/693 , H03K2217/0018
摘要: Embodiments include an apparatus, system, and method related to a switching circuit. In some embodiments, the switching circuit may include first switch including an n-channel field effect transistor (FET) in the signal path. The switching circuit may further include a second switch in shunt to the first switch. The second switch may include a discharge transistor to provide a discharge path for a body of a switch transistor. Other embodiments may be described and claimed.
摘要翻译: 实施例包括与开关电路相关的装置,系统和方法。 在一些实施例中,开关电路可以包括在信号路径中包括n沟道场效应晶体管(FET)的第一开关。 开关电路还可以包括分流到第一开关的第二开关。 第二开关可以包括放电晶体管,以为开关晶体管的主体提供放电路径。 可以描述和要求保护其他实施例。
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