公开(公告)号：US5475639A

公开(公告)日：1995-12-12

申请号：US215023

申请日：1994-03-21

Applicant: Akihiro Iwase ,  Teruo Seki ,  Shinji Nagai ,  Tadashi Ozawa

Inventor： Akihiro Iwase ,  Teruo Seki ,  Shinji Nagai ,  Tadashi Ozawa

IPC: G11C11/41 ,  G11C11/419 ,  G11C7/00

CPC classification number: G11C11/419

Abstract: Disclosed is a semiconductor memory device which operates based on voltages from a high voltage power source and a low voltage power source. A plurality of memory cells are formed in a memory cell array. Plural pairs of bit lines are connected to the memory cells to transfer data signals read from the memory cells. A sense amplifier, which has a pair of input terminals, amplifies the data signal. A level shifter is selectively connected to plural pairs of bit lines to shift the level of the data signal of a selected pair of bit lines to a level near the operation point of the sense amplifier, and supplies a resultant data signal to the sense amplifier. The level shifter includes a first transistor for receiving the data signal, and a plurality of second transistors connected between the first transistor and the low voltage power source. The first transistor has a first terminal to be supplied with the data signal, a second terminal and a control electrode for receiving a control signal for transferring the data signal to the sense amplifier. The second transistors are connected between the second terminal of the first transistor and the low voltage power source. The output of the second terminal of the first transistor is input to the input terminals of the sense amplifier.

Abstract translation: 公开了一种基于来自高压电源和低电压电源的电压进行工作的半导体存储器件。 在存储单元阵列中形成多个存储单元。 多对位线连接到存储器单元以传送从存储器单元读取的数据信号。 具有一对输入端的读出放大器放大数据信号。 电平移位器选择性地连接到多对位线，以将所选择的一对位线的数据信号的电平移动到读出放大器的操作点附近的电平，并将得到的数据信号提供给读出放大器。 电平移位器包括用于接收数据信号的第一晶体管和连接在第一晶体管和低电压电源之间的多个第二晶体管。 第一晶体管具有要提供数据信号的第一端子，第二端子和控制电极，用于接收用于将数据信号传送到读出放大器的控制信号。 第二晶体管连接在第一晶体管的第二端子和低压电源之间。 第一晶体管的第二端子的输出被输入到读出放大器的输入端。

公开(公告)号：US5187397A

公开(公告)日：1993-02-16

申请号：US853296

申请日：1992-03-18

Applicant: Miki Nishimori ,  Teruo Seki

Inventor： Miki Nishimori ,  Teruo Seki

IPC: G11C11/407 ,  G05F3/24 ,  G11C5/14 ,  G11C8/08 ,  G11C8/10 ,  G11C11/4074 ,  H03K19/094

CPC classification number: G05F3/24 ,  G11C11/4074 ,  G11C5/145 ,  G11C8/08 ,  G11C8/10

Abstract: An integrated semiconductor circuit has a boost circuit that may improve boost operation speed. The boost circuit employs a P-channel type transistor as a driver. The back gate of the P-channel type transistor is connected to a charge-up circuit so that the back gate may be charged to a predetermined level before a boost signal is applied to the driver.

公开(公告)号：US5747837A

公开(公告)日：1998-05-05

申请号：US763262

申请日：1996-12-10

Applicant: Akihiro Iwase ,  Tomio Nakano ,  Teruo Seki

Inventor： Akihiro Iwase ,  Tomio Nakano ,  Teruo Seki

IPC: H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H01L27/06

CPC classification number: H01L27/0259

Abstract: A semiconductor device with an expanded range of a recommended condition for an input voltage is disclosed. In embodiment, the semiconductor device having input protection on an input terminal thereto, includes: a semiconductor region having a first conducting type, first and second diffusion regions defined in the semiconductor region and respectively having a second conducting type, and a transistor formed by using the semiconductor region as a base, the first diffusion region as a collector, and the second diffusion region as an emitter. The first diffusion region is connected to one of a high-potential power supply and a low-potential power supply, the second diffusion region is connected to the input terminal, and the semiconductor region is connected to another power supply having a voltage high enough to reverse bias the junction between the semiconductor region and the first diffusion region.

Abstract translation: 公开了一种具有扩展的输入电压推荐条件范围的半导体器件。 在实施例中，在其输入端子上具有输入保护的半导体器件包括：具有限定在半导体区域中并且分别具有第二导电类型的第一导电类型，第一和第二扩散区域的半导体区域，以及通过使用 作为基底的半导体区域，第一扩散区域作为集电极，第二扩散区域作为发射极。 第一扩散区域连接到高电位电源和低电位电源中的一个，第二扩散区域连接到输入端子，并且半导体区域连接到具有足够高的电压的另一个电源， 反向偏置半导体区域和第一扩散区域之间的结。

公开(公告)号：US5307319A

公开(公告)日：1994-04-26

申请号：US844659

申请日：1992-04-02

Applicant: Takashi Kohketsu ,  Teruo Seki

Inventor： Takashi Kohketsu ,  Teruo Seki

IPC: G11C11/401 ,  G11C5/14 ,  G11C7/10 ,  G11C7/20 ,  G11C8/06 ,  H03K3/037 ,  G11C13/00

CPC classification number: G11C7/1093 ,  G11C5/147 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1087 ,  G11C7/20 ,  G11C8/06

Abstract: An initialization setting circuit (20) is adapted to set an initial condition of a latch circuit in a semiconductor device upon ON-set of the power supply, comprises a detecting circuit (TR1, TR2, R, 21) responsive to ON-set of power supply to detect the power source voltage (Vcc) reaching a given voltage, and an output level control circuit (22) responsive to the detecting signal output from the detecting circuit, for elevating up the level of an output signal of the initialization setting circuit to a high potential level or lowering the level of the output signal of the initialization setting circuit to a low potential level. By supplying the output signal controlled by said output level control circuit of the latch circuit as the power source voltage; the operation of the latch circuit is synchronized when the power source voltage is shut down, and a malfunction can be successfully prevented upon resetting of the power supply.

Abstract translation: PCT No.PCT / JP91 / 01143 Sec。 371日期：1992年4月2日 102（e）日期1992年4月2日PCT 1991年8月28日PCT PCT。 出版物WO92 / 0382500 日期：1992年3月5日。初始化设定电路（20）适于在电源接通时设定半导体器件中的锁存电路的初始状态，包括检测电路（TR1，TR2，R，21 ）响应于电源的接通以检测达到给定电压的电源电压（Vcc）;以及响应于从检测电路输出的检测信号的输出电平控制电路（22），用于将电平 初始化设置电路的输出信号变为高电位，或将初始化设定电路的输出信号的电平降低到低电位。 通过将由锁存电路的所述输出电平控制电路控制的输出信号作为电源电压提供; 当电源电压关闭时，锁存电路的操作是同步的，并且在电源复位时可以成功地防止故障。

公开(公告)号：US5122692A

公开(公告)日：1992-06-16

申请号：US645445

申请日：1991-01-24

Applicant: Teruo Seki

Inventor： Teruo Seki

IPC: H03K19/018 ,  H03K17/687 ,  H03K19/0175

CPC classification number: H03K17/6872 ,  H03K19/017518

Abstract: An input signal is received by a level shift circuit to generate a plurality of level-shifted output signals which have different shift amounts to each other. A switch circuit, selectively outputs the level-shifted output signals in response to a logic level of the input signal. The switch circuit selects a signal having a higher potential from the level-shifted output signals when the logic level of the input signal indicates a first level, and selects a signal having a lower potential from the level-shifted output signals when the logic level of the input signals indicates a second level.

公开(公告)号：US5097159A

公开(公告)日：1992-03-17

申请号：US312163

申请日：1989-02-21

Applicant: Teruo Seki ,  Akihiro Iwase ,  Sinzi Nagai

Inventor： Teruo Seki ,  Akihiro Iwase ,  Sinzi Nagai

IPC: H03K5/00 ,  H03K5/13

CPC classification number: H03K5/133 ,  H03K2005/00215

Abstract: A delay circuit having two or more first switching transistors connected in series between an output terminal and a power source line, and two or more second switching transistors connected in series between the output terminal and another power source line, the first and the second switching transistors operating in a complementary manner in response to an input signal, one or more nodes of each switching transistor being connected by one or more current paths each connecting at least one capacitor, whereby an input signal is transmitted to the output terminal at a specified interval defined by the capacitance of the capacitor.

公开(公告)号：US4571510A

公开(公告)日：1986-02-18

申请号：US535831

申请日：1983-09-26

Applicant: Teruo Seki ,  Takahiko Yamauchi ,  Keizo Aoyama

Inventor： Teruo Seki ,  Takahiko Yamauchi ,  Keizo Aoyama

IPC: G11C11/413 ,  G11C8/10 ,  H03K19/20 ,  G11C8/00 ,  H03K19/017 ,  H03K19/096

CPC classification number: G11C8/10

Abstract: A decoder circuit receives decoder inputs and producing decoder outputs. The decoder inputs are applied, as control inputs, to respective input transistors connected in parallel with each other. The outputs thereof are commonly connected to a node. The node is connected to a gate transistor and latch transistors. The gate transistor is operative to invert the level at the node momentarily every time the decoder circuit is switched from a nonselection state to a selection state. The latch transistors maintain the level at the node as the decoder output level.

Abstract translation: 解码器电路接收解码器输入并产生解码器输出。 解码器输入作为控制输入施加到彼此并联的相应输入晶体管。 其输出通常连接到节点。 节点连接到栅极晶体管和锁存晶体管。 每当解码器电路从非选择状态切换到选择状态时，栅极晶体管可操作地反转节点处的电平。 锁存晶体管将节点处的电平保持为解码器输出电平。

公开(公告)号：US5539335A

公开(公告)日：1996-07-23

申请号：US512913

申请日：1995-08-09

Applicant: Isamu Kobayashi ,  Teruo Seki

Inventor： Isamu Kobayashi ,  Teruo Seki

IPC: G11C11/409 ,  H03K17/687 ,  H03K19/003 ,  H03K19/0175 ,  H03K17/10

CPC classification number: H03K19/00315

Abstract: A output buffer circuit incorporates an output controller and voltage controller between a first and a second voltage potential to buffer the output of data produced by a semiconductor device. The output controller provides switching control signals to transistors in the voltage controller in order to prevent the first potential from being effected by the potential at the output of the output buffer.

Abstract translation: 输出缓冲器电路包括在第一和第二电压电位之间的输出控制器和电压控制器，以缓冲由半导体器件产生的数据的输出。 输出控制器向电压控制器中的晶体管提供开关控制信号，以防止第一电位受输出缓冲器输出端的电位的影响。

公开(公告)号：US5453956A

公开(公告)日：1995-09-26

申请号：US382408

申请日：1995-02-01

Applicant: Akihiro Iwase ,  Teruo Seki ,  Masaharu Kagohashi

Inventor： Akihiro Iwase ,  Teruo Seki ,  Masaharu Kagohashi

IPC: G11C11/419 ,  G11C7/10 ,  G11C11/409 ,  G11C11/413 ,  H03K5/02 ,  G11C11/40 ,  G11C13/00

CPC classification number: G11C7/1048

Abstract: A load generator is disclosed, which controls the voltage swing of the complementary logic signals generated in a semiconductor memory device. The load generator includes a first load circuit for controlling the potential levels of the signals appearing on a pair of complementary input signal lines. The first load circuit includes a first and second voltage dividers connected to the complementary input signal lines. Each of the first and second voltage dividers include a first voltage dividing transistor and a first voltage dividing resistive element connected in series between the semiconductor's low and high potential power supplies. The two first voltage dividing transistors are connected to each other in such a manner that a voltage, divided by one of the two transistors, is applied to the gate of the other transistor. The load generator further includes a second load circuit for controlling the potential levels of the signals appearing on a pair of complementary output signal lines. The second load circuit includes a third and fourth voltage dividing circuits associated with the first and second voltage dividing circuits and connected to the complementary output signal lines, respectively. Each of the third and fourth voltage dividing circuits includes a second voltage dividing transistor and a second voltage dividing resistive element, connected in series between the low and high potential power supplies.

Abstract translation: 公开了一种负载发生器，其控制在半导体存储器件中产生的互补逻辑信号的电压摆幅。 负载发生器包括用于控制出现在一对互补输入信号线上的信号的电位电平的第一负载电路。 第一负载电路包括连接到互补输入信号线的第一和第二分压器。 第一和第二分压器中的每一个包括串联连接在半导体的低电位和高电位电源之间的第一分压晶体管和第一分压电阻元件。 两个第一分压晶体管彼此连接，使得由两个晶体管中的一个分压的电压施加到另一个晶体管的栅极。 负载发生器还包括用于控制出现在一对互补输出信号线上的信号的电位电平的第二负载电路。 第二负载电路包括与第一和第二分压电路相关联并分别连接到互补输出信号线的第三和第四分压电路。 第三和第四分压电路中的每一个包括串联连接在低电位和高电位电源之间的第二分压晶体管和第二分压电阻元件。

公开(公告)号：US4809046A

公开(公告)日：1989-02-28

申请号：US915967

申请日：1986-10-06

Applicant: Keizo Aoyama ,  Takahiko Yamauchi ,  Teruo Seki

Inventor： Keizo Aoyama ,  Takahiko Yamauchi ,  Teruo Seki

IPC: G11C5/00 ,  G11C5/06 ,  G11C5/14 ,  G11C11/412 ,  H01L23/556 ,  H01L27/11 ,  H01L27/02

CPC classification number: G11C5/063 ,  G11C11/4125 ,  G11C5/005 ,  G11C5/14 ,  H01L23/556 ,  H01L27/1112 ,  H01L2924/0002 ,  Y10S257/927

Abstract: A static-type semiconductor memory device having a three-layer structure: gate-electrode wiring lines being formed from a first conductive layer of, for example, polycrystalline silicon; word lines, ground lines, and power supply lines being formed from a second conductive layer of, for example, aluminum; and bit lines being formed from a third conductive layer of, for example, aluminum. The bit lines extending in a column direction, and the ground lines extending in a row direction. Thus, providing an improved degree of integration, an improved operating speed, an improved manufacturing yield, and a countermeasure for soft errors due to alpha particles.

Abstract translation: 一种具有三层结构的静电型半导体存储器件：由例如多晶硅的第一导电层形成的栅电极布线; 字线，接地线和电源线由例如铝的第二导电层形成; 并且位线由例如铝的第三导电层形成。 位线沿列方向延伸，接地线沿行方向延伸。 因此，提供改进的集成度，改进的操作速度，改进的制造产量以及由于α粒子导致的软误差的对策。