摘要:
A semiconductor device may include gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating the gate electrodes and the interlayer insulating layers, a gate dielectric layer between the gate electrodes and the channel layer, a filling insulation that fills at least a portion of an interior of the channel layer, a charge fixing layer between the channel layer and the filling insulation and including a high-k material and/or a metal, and a conductive pad connected to the channel layer and on the filling insulation. The conductive pad may be physically separated from the charge fixing layer.
摘要:
In one embodiment, the semiconductor device includes a stack of alternating first interlayer insulating layers and gate electrode layers on a substrate. At least one of the gate electrode layers has a first portion and a second portion. The second portion forms an end portion of the at least one gate electrode layer, and a bottom surface of the second portion is at a lower level than a bottom surface of the first portion. A contact plug extends from the second portion.
摘要:
A semiconductor device includes a substrate, a plurality of gate electrodes extending in a first direction parallel to an upper surface of a substrate on the substrate, and alternately arranged with an interlayer insulating layer in a second direction perpendicular to the upper surface of the substrate, a vertical channel layer on a sidewall of a vertical channel hole extending in the second direction by penetrating through the plurality of gate electrodes and the interlayer insulating layer, and connected to the upper surface of the substrate, and a first gap-fill insulating layer formed in the vertical channel hole and including an outer wall contacting the vertical channel layer and an inner wall opposite the outer wall, wherein a part of the inner wall forms a striation extending in the second direction.
摘要:
In one embodiment, the semiconductor device includes a stack of alternating first interlayer insulating layers and gate electrode layers on a substrate. At least one of the gate electrode layers has a first portion and a second portion. The second portion forms an end portion of the at least one gate electrode layer, and a bottom surface of the second portion is at a lower level than a bottom surface of the first portion. A contact plug extends from the second portion.
摘要:
There is provided a diffuser for implementing a diffusing process in an equipment for manufacturing semiconductor devices to increase or maximize its productivity. The diffuser comprises a reaction pipe; a plate joined to the underside of the reaction pipe for sealing the reaction pipe and defining a work space therewithin. A plurality of wafers are disposed within the work space. A gas injection tube is provided for supplying a reactive gas to the work space. A plurality of plasma electrodes are disposed adjacent to the gas injection tube for applying high frequency power to a reactive gas to induce a plasma reaction. A protection member is adapted to cover a portion of the plasma electrodes inserted into the reaction tube located under the plurality of wafers, for preventing a substantial amount of polymer from being formed under the reactive tube due to a plasma reaction in the reactive gases
摘要:
A stack structure includes conductive layer patterns and interlayer insulating layer patterns alternately stacked on one another. A channel hole penetrates the stack structure. A dielectric layer is disposed on a sidewall of the channel hole. A channel layer is disposed on the dielectric layer and in the channel hole. A passivation layer is disposed on the channel layer and in the channel hole. The channel layer is interposed between the passivation layer and the dielectric layer. An air gap is surrounded by the passivation layer. A width of the air gap is larger than a width of the passivation layer.
摘要:
A semiconductor device may include gate electrodes and interlayer insulating layers alternately stacked on a substrate, a channel layer penetrating the gate electrodes and the interlayer insulating layers, a gate dielectric layer between the gate electrodes and the channel layer, a filling insulation that fills at least a portion of an interior of the channel layer, a charge fixing layer between the channel layer and the filling insulation and including a high-k material and/or a metal, and a conductive pad connected to the channel layer and on the filling insulation. The conductive pad may be physically separated from the charge fixing layer.
摘要:
Provided are semiconductor devices including a semiconductor substrate, an insulating layer including a contact hole through which the semiconductor substrate is exposed, and a polysilicon layer filling the contact hole. The polysilicon layer is doped with impurities and includes an impurity-diffusion prevention layer. In the semiconductor devices, the impurities included in the polysilicon layer do not diffuse into the insulating layer and the semiconductor substrate due to the impurity-diffusion prevention layers.
摘要:
A stack structure includes conductive layer patterns and interlayer insulating layer patterns alternately stacked on one another. A channel hole penetrates the stack structure. A dielectric layer is disposed on a sidewall of the channel hole. A channel layer is disposed on the dielectric layer and in the channel hole. A passivation layer is disposed on the channel layer and in the channel hole. The channel layer is interposed between the passivation layer and the dielectric layer. An air gap is surrounded by the passivation layer. A width of the air gap is larger than a width of the passivation layer.
摘要:
A semiconductor device includes a stack structure on a substrate, the stack structure including interlayer insulating layers and first gate electrodes alternately stacked on each other, a semiconductor layer in an opening penetrating through the stack structure, a first dielectric layer between the semiconductor layer and the stack structure, and a lower pattern closer to the substrate than to the first gate electrodes in the stack structure, the lower pattern including a first surface facing the first dielectric layer, and a second surface facing the stack structure, the second surface defining an acute angle with the first surface, wherein the first dielectric layer includes a first portion facing the stack structure, and a second portion facing the first surface of the lower pattern, the second portion having a thickness greater than a thickness of the first portion.