公开(公告)号：US10103142B2

公开(公告)日：2018-10-16

申请号：US15076952

申请日：2016-03-22

申请人： Sug-hyun Sung ,  Jung-gun You ,  Gi-gwan Park

发明人： Sug-hyun Sung ,  Jung-gun You ,  Gi-gwan Park

IPC分类号： H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L21/762 ,  H01L21/8234

摘要： Integrated circuit devices are provided. The devices may include first and second fin-shaped channel regions protruding from a substrate, and the first and second fin-shaped channel regions may define a recess therebetween. The devices may also include an isolation layer in a lower portion of the recess. The isolation layer may include a first stress liner extending along a side of the first fin-shaped channel region, a second stress liner extending along a side of the second fin-shaped channel region and an insulation liner between the first stress liner and the side of the first fin-shaped channel region and between the second stress liner and the side of the second fin-shaped channel region. The devices may further include a gate insulation layer on surfaces of upper portions of the first and second fin-shaped channel regions and a gate electrode layer on the gate insulation layer.

公开(公告)号：US20070264810A1

公开(公告)日：2007-11-15

申请号：US11783181

申请日：2007-04-06

申请人： Ki-Chul Kim ,  Hwa-Sung Rhee ,  Sug-Hyun Sung ,  Sang-Doo Kim

发明人： Ki-Chul Kim ,  Hwa-Sung Rhee ,  Sug-Hyun Sung ,  Sang-Doo Kim

IPC分类号： H01L21/3205 ,  H01L21/4763

CPC分类号： H01L29/7848 ,  H01L21/28061 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66545 ,  H01L29/66636

摘要： A semiconductor device and a method of manufacturing the same, including obtaining a semiconductor substrate, forming a device isolating layer having a depression part and a protrusion part in the semiconductor substrate, forming a gate insulating layer and a gate electrode on the semiconductor substrate, forming a spacer in communication with the gate electrode, removing a portion of the semiconductor substrate to form at least one substrate recess region in an upper surface of the semiconductor substrate and at least one substrate remaining portion extending to a same height as the semiconductor substrate, so that the substrate remaining portion forms a sidewall of the substrate recess region and is in communication with the device isolating layer, and forming a substrate epitaxial layer in the substrate recess region.

摘要翻译： 一种半导体器件及其制造方法，包括获得半导体衬底，在半导体衬底中形成具有凹陷部分和突出部分的器件隔离层，在半导体衬底上形成栅极绝缘层和栅电极，形成 与所述栅电极连通的间隔物，去除所述半导体衬底的一部分以在所述半导体衬底的上表面中形成至少一个衬底凹部区域，以及至少一个衬底剩余部分延伸到与所述半导体衬底相同的高度，因此 衬底剩余部分形成衬底凹陷区域的侧壁并且与器件隔离层连通，并且在衬底凹槽区域中形成衬底外延层。

公开(公告)号：US20160351565A1

公开(公告)日：2016-12-01

申请号：US15076952

申请日：2016-03-22

申请人： Sug-hyun SUNG ,  Jung-gun YOU ,  Gi-gwan PARK

发明人： Sug-hyun SUNG ,  Jung-gun YOU ,  Gi-gwan PARK

IPC分类号： H01L27/088 ,  H01L29/06 ,  H01L29/78

CPC分类号： H01L27/0886 ,  H01L21/76229 ,  H01L21/823412 ,  H01L21/823431 ,  H01L29/0649 ,  H01L29/165 ,  H01L29/66818 ,  H01L29/7843 ,  H01L29/7846 ,  H01L29/7848 ,  H01L29/7854

摘要： Integrated circuit devices are provided. The devices may include first and second fin-shaped channel regions protruding from a substrate, and the first and second fin-shaped channel regions may define a recess therebetween. The devices may also include an isolation layer in a lower portion of the recess. The isolation layer may include a first stress liner extending along a side of the first fin-shaped channel region, a second stress liner extending along a side of the second fin-shaped channel region and an insulation liner between the first stress liner and the side of the first fin-shaped channel region and between the second stress liner and the side of the second fin-shaped channel region. The devices may further include a gate insulation layer on surfaces of upper portions of the first and second fin-shaped channel regions and a gate electrode layer on the gate insulation layer.

摘要翻译： 提供集成电路设备。 这些装置可以包括从基板突出的第一和第二鳍形通道区域，并且第一和第二鳍状通道区域可以在其间限定凹部。 这些装置还可以包括在凹部的下部中的隔离层。 隔离层可以包括沿着第一鳍状通道区域的一侧延伸的第一应力衬垫，沿着第二鳍状沟道区域的侧面延伸的第二应力衬垫和在第一应力衬垫和侧面之间的绝缘衬垫 并且在第二应力衬垫和第二鳍状沟道区域的侧面之间。 器件还可以包括在第一和第二鳍状沟道区的上部表面上的栅极绝缘层和栅极绝缘层上的栅极电极层。

公开(公告)号：US20180006032A1

公开(公告)日：2018-01-04

申请号：US15708512

申请日：2017-09-19

申请人： Jung-Gun You ,  Sug-Hyun Sung

发明人： Jung-Gun You ,  Sug-Hyun Sung

IPC分类号： H01L27/088 ,  H01L21/8234 ,  H01L29/06

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/7854

摘要： Provided is a semiconductor device and a fabricating method thereof. The semiconductor device includes a first trench having a first depth to define a fin, a second trench formed directly adjacent the first trench having a second depth that is greater than the first depth, a field insulation layer filling a portion of the first trench and a portion of the second trench, and a protrusion structure protruding from a bottom of the first trench and being lower than a surface of the field insulation layer.

公开(公告)号：US20160218180A1

公开(公告)日：2016-07-28

申请号：US14968999

申请日：2015-12-15

申请人： Jung-Gun You ,  Se-Wan PARK ,  Seung-Woo DO ,  In-Won PARK ,  Sug-Hyun SUNG

发明人： Jung-Gun You ,  Se-Wan PARK ,  Seung-Woo DO ,  In-Won PARK ,  Sug-Hyun SUNG

IPC分类号： H01L29/10 ,  H01L29/417 ,  H01L21/762 ,  H01L29/66

CPC分类号： H01L29/66545 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/76224 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/785

摘要： A method for fabricating a semiconductor device is provided. The method includes forming a first fin-shaped pattern including an upper part and a lower part on a substrate, forming a second fin-shaped pattern by removing a part of the upper part of the first fin-shaped pattern, forming a dummy gate electrode intersecting with the second fin-shaped pattern on the second fin-shaped pattern, and forming a third fin-shaped pattern by removing a part of an upper part of the second fin-shaped pattern after forming the dummy gate electrode, wherein a width of the upper part of the second fin-shaped pattern is smaller than a width of the upper part of the first fin-shaped pattern and is greater than a width of an upper portion of the third fin-shaped pattern.

摘要翻译： 提供一种制造半导体器件的方法。 该方法包括在衬底上形成包括上部和下部的第一鳍状图案，通过去除第一鳍状图案的上部的一部分形成第二鳍状图案，形成虚拟栅电极 与第二鳍状图案上的第二鳍状图案相交，并且在形成虚拟栅电极之后，通过去除第二鳍状图案的上部的一部分来形成第三鳍​​状图案，其中宽度 第二鳍状图案的上部小于第一鳍状图案的上部的宽度，并且大于第三鳍状图案的上部的宽度。

公开(公告)号：US20160190131A1

公开(公告)日：2016-06-30

申请号：US14976082

申请日：2015-12-21

申请人： Jung-Gun YOU ,  Sug-Hyun SUNG

发明人： Jung-Gun YOU ,  Sug-Hyun SUNG

IPC分类号： H01L27/088 ,  H01L29/06

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/7854

摘要： Provided is a semiconductor device and a fabricating method thereof. The semiconductor device includes a first trench having a first depth to define a fin, a second trench formed directly adjacent the first trench having a second depth that is greater than the first depth, a field insulation layer filling a portion of the first trench and a portion of the second trench, and a protrusion structure protruding from a bottom of the first trench and being lower than a surface of the field insulation layer.

摘要翻译： 提供一种半导体器件及其制造方法。 半导体器件包括具有第一深度以限定翅片的第一沟槽，与第一沟槽直接相邻形成的第二沟槽，其具有大于第一深度的第二深度，填充第一沟槽的一部分的场绝缘层和 第二沟槽的一部分，以及从第一沟槽的底部突出并且低于场隔离层的表面的突起结构。

公开(公告)号：US09620406B2

公开(公告)日：2017-04-11

申请号：US14968999

申请日：2015-12-15

申请人： Jung-Gun You ,  Se-Wan Park ,  Seung-Woo Do ,  In-Won Park ,  Sug-Hyun Sung

发明人： Jung-Gun You ,  Se-Wan Park ,  Seung-Woo Do ,  In-Won Park ,  Sug-Hyun Sung

IPC分类号： H01L21/762 ,  H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L29/165

CPC分类号： H01L29/66545 ,  H01L21/30604 ,  H01L21/3085 ,  H01L21/76224 ,  H01L29/165 ,  H01L29/41766 ,  H01L29/66795 ,  H01L29/6681 ,  H01L29/66818 ,  H01L29/7848 ,  H01L29/785

摘要： A method for fabricating a semiconductor device is provided. The method includes forming a first fin-shaped pattern including an upper part and a lower part on a substrate, forming a second fin-shaped pattern by removing a part of the upper part of the first fin-shaped pattern, forming a dummy gate electrode intersecting with the second fin-shaped pattern on the second fin-shaped pattern, and forming a third fin-shaped pattern by removing a part of an upper part of the second fin-shaped pattern after forming the dummy gate electrode, wherein a width of the upper part of the second fin-shaped pattern is smaller than a width of the upper part of the first fin-shaped pattern and is greater than a width of an upper portion of the third fin-shaped pattern.

公开(公告)号：US20160204106A1

公开(公告)日：2016-07-14

申请号：US14989876

申请日：2016-01-07

申请人： Jung-Gun YOU ,  Sug-Hyun SUNG ,  Se-Wan PARK

发明人： Jung-Gun YOU ,  Sug-Hyun SUNG ,  Se-Wan PARK

IPC分类号： H01L27/088 ,  H01L29/423 ,  H01L29/06

CPC分类号： H01L27/0886 ,  H01L21/823431 ,  H01L21/823481 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/42376

摘要： A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes a fin which comprises long sides and a first short side, a first trench which is immediately adjacent the first short side of the fin and has a first depth, a second trench which is immediately adjacent the first trench and has a second depth greater than the first depth, a first protrusion structure which protrudes from a bottom of the first trench and extends side by side with the first short side, and a gate which is formed on the first protrusion structure to extend side by side with the first short side.

摘要翻译： 提供半导体器件及其制造方法。 该半导体器件包括一个翅片，它包括长边和第一短边，第一沟槽紧邻翅片的第一短边并且具有第一深度，第二沟槽紧邻第一沟槽并具有第二沟槽 深度大于第一深度的第一突出结构，从第一沟槽的底部突出并与第一短边并排延伸的第一突起结构，以及形成在第一突起结构上并与第一突起并排延伸的第一突起结构 短边