公开(公告)号：US5202849A

公开(公告)日：1993-04-13

申请号：US929488

申请日：1992-08-18

Applicant: Shigeki Nozaki

Inventor： Shigeki Nozaki

IPC: H01L27/108

CPC classification number: H01L27/10817 ,  H01L27/10808

Abstract: A dynamic random access memory comprises a substrate, a transfer transistor provided on the substrate, a memory cell capacitor provided on the substrate in contact with a first diffusion region formed in the substrate, a first conductor pattern provided on the substrate to extend in a first direction as a word line, a first insulator layer provided on the substrate to bury the memory cell capacitor and the first conductor pattern, a first contact hole provided on the first insulator layer to expose a second diffusion region formed in the substrate, a second conductor pattern provided on the first insulator layer to extend in a second direction, passing above the memory cell capacitor and making a contact with the second diffusion region at the first contact hole, a second insulator layer provided on the second conductor pattern, a second contact hole provided on the second insulator layer at a part thereof that locates above the memory cell capacitor to expose the upper major surface of the second conductor pattern, and a third conductor pattern provided on the second insulator layer to extend in the second direction substantially coincident with the first conductor pattern as a bit line of the dynamic random access memory, wherein the third conductor pattern makes a contact with the second conductor pattern at the second contact hole.

Abstract translation: 动态随机存取存储器包括：衬底，设置在衬底上的转移晶体管，设置在与衬底中形成的第一扩散区相接触的衬底上的存储单元电容器;设置在衬底上的第一导体图案， 方向作为字线，设置在衬底上以埋置存储单元电容器和第一导体图案的第一绝缘体层，设置在第一绝缘体层上以暴露形成在衬底中的第二扩散区域的第一接触孔，第二导体 图案设置在第一绝缘体层上以在第二方向上延伸，在存储单元电容器上方通过并与第一接触孔处的第二扩散区域接触，设置在第二导体图案上的第二绝缘体层，第二接触孔 设置在位于存储单元电容器上方的第二绝缘体层上，以露出上主表面o f的第二导体图案，以及设置在第二绝缘体层上的第三导体图案，以在第二方向上与作为动态随机存取存储器的位线的第一导体图案基本一致，其中第三导体图案与 在第二接触孔处的第二导体图案。

公开(公告)号：US4535423A

公开(公告)日：1985-08-13

申请号：US447660

申请日：1982-12-07

Applicant: Shigeki Nozaki ,  Hatsuo Miyahara

Inventor： Shigeki Nozaki ,  Hatsuo Miyahara

IPC: G11C11/404 ,  G11C5/14 ,  G11C11/401 ,  G11C11/4074 ,  G11C5/10

CPC classification number: G11C5/14 ,  G11C11/4074

Abstract: A semiconductor memory device which includes a plurality of memory cells each having a capacitor, and peripheral circuits of the memory cells, integrated on a semiconductor substrate. Each capacitor has a storage electrode and an electrode opposite to the storage electrode, the opposite electrode being connected to a ground line, wherein, the ground line connected to the opposite electrode of each capacitor is separated from the other ground lines connected to the peripheral circuits. All of the ground lines are connected to a common portion having an impedance lower than the impedance of each ground line, whereby data stored in the capacitors is prevented from being destroyed.

Abstract translation: 一种半导体存储器件，包括多个存储单元，每个存储单元均具有电容器，以及集成在半导体衬底上的存储单元的外围电路。 每个电容器具有存储电极和与存储电极相对的电极，相对电极连接到接地线，其中连接到每个电容器的相对电极的接地线与连接到外围电路的其它接地线分离 。 所有接地线都连接到具有比每个接地线的阻抗低的阻抗的公共部分，从而防止存储在电容器中的数据被破坏。

公开(公告)号：US4511997A

公开(公告)日：1985-04-16

申请号：US439507

申请日：1982-11-05

Applicant: Shigeki Nozaki ,  Yoshihiro Takemae ,  Tomio Nakano

Inventor： Shigeki Nozaki ,  Yoshihiro Takemae ,  Tomio Nakano

IPC: G11C11/419 ,  G11C11/34 ,  G11C11/401 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/40

CPC classification number: G11C11/4096

Abstract: A metal-insulator semiconductor dynamic memory device including sense amplifiers arrayed on a semiconductor substrate and divided into a plurality of sense amplifier groups. Column decoders are provided, one decoder for each sense amplifier group, each sense amplifier group being selected by the column decoder. One or more control signal lines for simultaneously selecting the output signals of at least two sense amplifiers in the sense amplifier group selected by the column decoder, a plurality of data buses for transferring the output signals of at least two sense amplifiers selected by one or more control signal lines, are included in the memory device. All of the sense amplifiers have the control signal lines and the data buses in common.

Abstract translation: 一种金属绝缘体半导体动态存储器件，包括排列在半导体衬底上并分成多个读出放大器组的读出放大器。 提供列解码器，每个读出放大器组的一个解码器，每个读出放大器组由列解码器选择。 一个或多个控制信号线，用于同时选择由列解码器选择的读出放大器组中的至少两个读出放大器的输出信号;多个数据总线，用于传送由一个或多个选择的至少两个读出放大器的输出信号 控制信号线被包括在存储器件中。 所有的读出放大器都具有控制信号线和数据总线。

公开(公告)号：US4384348A

公开(公告)日：1983-05-17

申请号：US221329

申请日：1980-12-29

Applicant: Shigeki Nozaki

Inventor： Shigeki Nozaki

IPC: G11C29/56 ,  G11C13/00

CPC classification number: G11C29/56

Abstract: A semiconductor memory testing device and testing method comprises an address pattern generator which successively generates an address pattern which specifies the X-Y addresses of each memory cell of a semiconductor memory device which is to be tested, an address changeover or swapping device which makes access to the semiconductor memory device with the address pattern supplied by the address pattern generator during normal operation mode, and addresses interchanged during swap operation mode, a comparator which compares data from the semiconductor memory device with an expected value to detect hardware error, and a fail memory device which stores information concerning the existence hardware error in each of the memory cells of the semiconductor memory device in an address region corresponding to that of the bad cell of the semiconductor memory device. The semiconductor memory device and the fail memory device both receive common X-Y addresses from the address changeover or swapping device. The comparator preheated from comparing by a signal supplied from said fail memory device for the memory cells of the semiconductor memory device corresponding to the memory cells of the fail memory device which have information stored therein indicating the existence of hardware errors.

Abstract translation: 半导体存储器测试装置和测试方法包括地址模式生成器，其连续地生成指定要测试的半导体存储器件的每个存储器单元的XY地址的地址模式，访问所述测试的地址切换或交换设备 半导体存储器件，其具有在正常操作模式期间由地址模式发生器提供的地址模式，以及在交换操作模式期间交换的地址;将来自半导体存储器件的数据与预期值进行比较以检测硬件错误的比较器，以及故障存储器件 其存储与半导体存储器件的坏单元的地址区域相对应的与半导体存储器件的每个存储单元中的存在硬件错误有关的信息。 半导体存储器件和故障存储器件都从地址转换或交换器件接收公共X-Y地址。 所述比较器从由所述故障存储器件提供的信号与所述半导体存储器件的存储器单元相对应的信号进行比较，所述存储单元对应于存储有指示存在硬件错误的存储在其中的信息的故障存储器件的存储器单元。

公开(公告)号：US5119335A

公开(公告)日：1992-06-02

申请号：US711402

申请日：1991-06-05

Applicant: Shigeki Nozaki

Inventor： Shigeki Nozaki

IPC: G01R31/30 ,  G11C11/419 ,  G11C29/50

CPC classification number: G11C29/50 ,  G11C11/419 ,  G01R31/30 ,  G11C11/41

Abstract: A semiconductor memory device including a pair of bit lines, a memory cell provided between the pair of bit lines, and a potential difference control device connected to the pair of bit lines. The bit lines include a potential difference therebetween when information stored in the memory cell is read out. The potential difference control device has a transistor control for receiving a first control signal and for responding thereto; thereby, increasing the potential difference between the pair of bit lines up to a predetermined level so as to provide a high speed read-operation and to reliably discriminate a "good" or a "no good" reading when subjected to a screening test.

Abstract translation: 一种半导体存储器件，包括一对位线，设置在所述一对位线之间的存储单元和连接到所述一对位线的电位差控制器件。 当存储在存储单元中的信息被读出时，位线包括它们之间的电位差。 电位差控制装置具有用于接收第一控制信号并对其进行响应的晶体管控制; 从而将一对位线之间的电位差增加到预定水平，以便提供高速读取操作，并且在进行筛选测试时可靠地区分“良好”或“不好”读数。

公开(公告)号：US4602356A

公开(公告)日：1986-07-22

申请号：US445921

申请日：1982-12-01

Applicant: Shigeki Nozaki ,  Yoshihiro Takemae ,  Seiji Enomoto

Inventor： Shigeki Nozaki ,  Yoshihiro Takemae ,  Seiji Enomoto

IPC: G11C11/41 ,  G11C7/00 ,  G11C8/00 ,  G11C8/18 ,  G11C11/407 ,  G11C11/408 ,  G11C11/413

CPC classification number: G11C8/18

Abstract: A semiconductor memory device operates under a so-called address multiplex access method. A row part of the device is enabled by receiving a row address strobe (RAS) signal. A column part of the device is enabled by simultaneously receiving both a column address strobe (CAS) signal and a timing control signal supplied from the row part during its enable state. A column address buffer in the column part is enabled by simultaneously receiving both the CAS signal and a timing control signal. The timing control signal is produced from a circuit when it detects and holds the RAS signal.

Abstract translation: 半导体存储器件以所谓的地址复用存取方式工作。 器件的一部分通过接收行地址选通（＆upbar＆R）信号来使能。 器件的列部分通过在其使能状态期间同时接收列地址选通（＆upbar＆C）信号和从行部分提供的定时控制信号来启用。 列部分中的列地址缓冲器通过同时接收＆upbar＆C信号和定时控制信号而被使能。 定时控制信号从电路产生，当它检测并保持＆amp; R＆R信号。

公开(公告)号：US4570088A

公开(公告)日：1986-02-11

申请号：US510183

申请日：1983-07-01

Applicant: Shigeki Nozaki ,  Tomio Nakano ,  Katsuhiko Kabashima

Inventor： Shigeki Nozaki ,  Tomio Nakano ,  Katsuhiko Kabashima

IPC: G11C11/401 ,  G11C5/14 ,  G11C11/407 ,  G11C11/408 ,  G11C11/409 ,  G11C11/4094 ,  H01L27/10 ,  H03K17/22 ,  H03K19/096

CPC classification number: G11C11/4085 ,  G11C11/4094 ,  G11C5/145

Abstract: A semiconductor device, provided with a buffer, which comprises a first transistor for pulling up the output terminal voltage, a second transistor for pulling down the output terminal voltage, and a charge-pumping circuit for maintaining the output terminal voltage at a level higher than the power source voltage by charge pumping when the output terminal voltage is at a high level. The semiconductor device further comprises a circuit for pulling down the output terminal voltage during the period from when power is supplied to when an input signal is supplied to the buffer.

Abstract translation: 一种具有缓冲器的半导体器件，包括用于提升输出端电压的第一晶体管，用于下拉输出端电压的第二晶体管，以及用于将输出端电压维持在高于 当输出端子电压处于高电平时，电源电压通过电荷泵浦。 该半导体器件还包括一个电路，用于在从供电到输入信号提供给缓冲器的时间段期间，降低输出端电压。

公开(公告)号：US4970693A

公开(公告)日：1990-11-13

申请号：US484474

申请日：1990-02-23

Applicant: Shigeki Nozaki ,  Tsuyoshi Ohira ,  Masaru Satoh ,  Tomio Nakano ,  Yoshihiro Takemae

Inventor： Shigeki Nozaki ,  Tsuyoshi Ohira ,  Masaru Satoh ,  Tomio Nakano ,  Yoshihiro Takemae

IPC: G11C11/409 ,  G11C7/22 ,  G11C8/18 ,  G11C11/40 ,  G11C11/413

CPC classification number: G11C7/22 ,  G11C8/18

Abstract: A semiconductor memory device is connected to a power source and includes a reference potential line connected to receive a reference potential from the power source. An input circuit is connected to the reference potential line and receives an external input signal having a logic level defined in reference to the reference potential to be supplied to the source potential line. The output circuit has an external output terminal which is connected to the reference potential line. The output circuit is for generating an output to the external output terminal. An inhibiting circuit inhibits a response to the external input signal of the input circuit for a predetermined period during which the output of the output circuit changes.

Abstract translation: 半导体存储器件连接到电源，并且包括连接以从电源接收参考电位的参考电位线。 输入电路连接到参考电位线，并接收具有参考参考电位定义的逻辑电平的外部输入信号以提供给源极电位线。 输出电路具有连接到参考电位线的外部输出端子。 输出电路用于产生到外部输出端子的输出。 禁止电路在输出电路的输出变化的预定时间段期间阻止对输入电路的外部输入信号的响应。

公开(公告)号：US4546457A

公开(公告)日：1985-10-08

申请号：US439591

申请日：1982-11-05

Applicant: Shigeki Nozaki ,  Yoshihiro Takemae

Inventor： Shigeki Nozaki ,  Yoshihiro Takemae

IPC: G11C11/419 ,  G11C7/06 ,  G11C11/407 ,  G11C11/408 ,  G11C11/409 ,  G11C11/40

CPC classification number: G11C11/4087 ,  G11C7/06

Abstract: A metal-insulator semiconductor dynamic memory device comprising sense amplifiers arrayed on a semiconductor substrate and column decoders. Each of the column decode being provided for a plurality of sense amplifiers and selecting one or more sense amplifiers from the plurality of sense amplifiers, the column decoders being dispersed on both sides of the arrayed sense amplifiers. A plurality of control signal lines which, in order to select the sense amplifiers, control gate elements connected between bit lines connected to the sense amplifiers and data bus lines and which are disposed on both sides of the arrayed sense amplifiers. Conducting lines are also disposed between the sense amplifiers and deliver signals from the control signal lines, for selecting sense amplifiers to the gate elements on the opposite side of the control signal lines with regard to the arrayed sense amplifiers.

Abstract translation: 包括排列在半导体衬底和列解码器上的读出放大器的金属 - 绝缘体半导体动态存储器件。 每个列解码被提供给多个读出放大器并且从多个读出放大器中选择一个或多个感测放大器，列解码器分散在排列的读出放大器的两侧。 多个控制信号线，为了选择读出放大器，控制栅极元件连接在连接到读出放大器的位线和数据总线之间，并且布置在阵列读出放大器的两侧。 传导线还设置在感测放大器之间并且传送来自控制信号线的信号，用于选择感测放大器到控制信号线相对于阵列读出放大器的相反侧的门元件。

公开(公告)号：US4447745A

公开(公告)日：1984-05-08

申请号：US322719

申请日：1981-11-18

Applicant: Yoshihiro Takemae ,  Seiji Enomoto ,  Shigeki Nozaki ,  Tsutomu Mezawa ,  Katsuhiko Kabashima

Inventor： Yoshihiro Takemae ,  Seiji Enomoto ,  Shigeki Nozaki ,  Tsutomu Mezawa ,  Katsuhiko Kabashima

IPC: G11C11/417 ,  G06F1/04 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/418 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/096 ,  H03K5/135

CPC classification number: G11C11/4076 ,  G11C11/418 ,  H03K19/01735 ,  H03K19/01855

Abstract: A semiconductor circuit used as a buffer circuit having an input stage circuit for receiving an input clock signal and an inverted input clock signal, a bootstrap circuit including a transistor for receiving the output of the input stage circuit and for maintaining the gate voltage of the transistor at a high level during the standby period, and an output circuit, including a transistor which is switched on and off by the output of the bootstrap circuit, for generating an output clock signal; the semiconductor circuit further comprising a current leak circuit for maintaining, during the standby period, the voltage of a point in the semiconductor circuit which is charged during the standby period at the value corresponding to the voltage of the power source, whereby the delay of the output clock signal, caused of the fluctuation by the voltage of the power supply during the standby period, is improved and then the high speed access time in the dynamic memory is carried out.

Abstract translation: 一种用作缓冲电路的半导体电路，具有用于接收输入时钟信号和反相输入时钟信号的输入级电路，自举电路包括用于接收输入级电路的输出并保持晶体管的栅极电压的晶体管 在待机期间处于高电平;以及输出电路，包括由所述自举电路的输出接通和断开的晶体管，用于产生输出时钟信号; 所述半导体电路还包括电流泄漏电路，用于在所述待机期间保持所述半导体电路中在所述待机期间中以与所述电源的电压对应的值被充电的点的电压，由此所述延迟 在待机期间由电源的电压引起的输出时钟信号被提高，然后执行动态存储器中的高速访问时间。