公开(公告)号：US4602356A

公开(公告)日：1986-07-22

申请号：US445921

申请日：1982-12-01

Applicant: Shigeki Nozaki ,  Yoshihiro Takemae ,  Seiji Enomoto

Inventor： Shigeki Nozaki ,  Yoshihiro Takemae ,  Seiji Enomoto

IPC: G11C11/41 ,  G11C7/00 ,  G11C8/00 ,  G11C8/18 ,  G11C11/407 ,  G11C11/408 ,  G11C11/413

CPC classification number: G11C8/18

Abstract: A semiconductor memory device operates under a so-called address multiplex access method. A row part of the device is enabled by receiving a row address strobe (RAS) signal. A column part of the device is enabled by simultaneously receiving both a column address strobe (CAS) signal and a timing control signal supplied from the row part during its enable state. A column address buffer in the column part is enabled by simultaneously receiving both the CAS signal and a timing control signal. The timing control signal is produced from a circuit when it detects and holds the RAS signal.

Abstract translation: 半导体存储器件以所谓的地址复用存取方式工作。 器件的一部分通过接收行地址选通（＆upbar＆R）信号来使能。 器件的列部分通过在其使能状态期间同时接收列地址选通（＆upbar＆C）信号和从行部分提供的定时控制信号来启用。 列部分中的列地址缓冲器通过同时接收＆upbar＆C信号和定时控制信号而被使能。 定时控制信号从电路产生，当它检测并保持＆amp; R＆R信号。

公开(公告)号：US4970693A

公开(公告)日：1990-11-13

申请号：US484474

申请日：1990-02-23

Applicant: Shigeki Nozaki ,  Tsuyoshi Ohira ,  Masaru Satoh ,  Tomio Nakano ,  Yoshihiro Takemae

Inventor： Shigeki Nozaki ,  Tsuyoshi Ohira ,  Masaru Satoh ,  Tomio Nakano ,  Yoshihiro Takemae

IPC: G11C11/409 ,  G11C7/22 ,  G11C8/18 ,  G11C11/40 ,  G11C11/413

CPC classification number: G11C7/22 ,  G11C8/18

Abstract: A semiconductor memory device is connected to a power source and includes a reference potential line connected to receive a reference potential from the power source. An input circuit is connected to the reference potential line and receives an external input signal having a logic level defined in reference to the reference potential to be supplied to the source potential line. The output circuit has an external output terminal which is connected to the reference potential line. The output circuit is for generating an output to the external output terminal. An inhibiting circuit inhibits a response to the external input signal of the input circuit for a predetermined period during which the output of the output circuit changes.

Abstract translation: 半导体存储器件连接到电源，并且包括连接以从电源接收参考电位的参考电位线。 输入电路连接到参考电位线，并接收具有参考参考电位定义的逻辑电平的外部输入信号以提供给源极电位线。 输出电路具有连接到参考电位线的外部输出端子。 输出电路用于产生到外部输出端子的输出。 禁止电路在输出电路的输出变化的预定时间段期间阻止对输入电路的外部输入信号的响应。

公开(公告)号：US4546457A

公开(公告)日：1985-10-08

申请号：US439591

申请日：1982-11-05

Applicant: Shigeki Nozaki ,  Yoshihiro Takemae

Inventor： Shigeki Nozaki ,  Yoshihiro Takemae

IPC: G11C11/419 ,  G11C7/06 ,  G11C11/407 ,  G11C11/408 ,  G11C11/409 ,  G11C11/40

CPC classification number: G11C11/4087 ,  G11C7/06

Abstract: A metal-insulator semiconductor dynamic memory device comprising sense amplifiers arrayed on a semiconductor substrate and column decoders. Each of the column decode being provided for a plurality of sense amplifiers and selecting one or more sense amplifiers from the plurality of sense amplifiers, the column decoders being dispersed on both sides of the arrayed sense amplifiers. A plurality of control signal lines which, in order to select the sense amplifiers, control gate elements connected between bit lines connected to the sense amplifiers and data bus lines and which are disposed on both sides of the arrayed sense amplifiers. Conducting lines are also disposed between the sense amplifiers and deliver signals from the control signal lines, for selecting sense amplifiers to the gate elements on the opposite side of the control signal lines with regard to the arrayed sense amplifiers.

Abstract translation: 包括排列在半导体衬底和列解码器上的读出放大器的金属 - 绝缘体半导体动态存储器件。 每个列解码被提供给多个读出放大器并且从多个读出放大器中选择一个或多个感测放大器，列解码器分散在排列的读出放大器的两侧。 多个控制信号线，为了选择读出放大器，控制栅极元件连接在连接到读出放大器的位线和数据总线之间，并且布置在阵列读出放大器的两侧。 传导线还设置在感测放大器之间并且传送来自控制信号线的信号，用于选择感测放大器到控制信号线相对于阵列读出放大器的相反侧的门元件。

公开(公告)号：US4447745A

公开(公告)日：1984-05-08

申请号：US322719

申请日：1981-11-18

Applicant: Yoshihiro Takemae ,  Seiji Enomoto ,  Shigeki Nozaki ,  Tsutomu Mezawa ,  Katsuhiko Kabashima

Inventor： Yoshihiro Takemae ,  Seiji Enomoto ,  Shigeki Nozaki ,  Tsutomu Mezawa ,  Katsuhiko Kabashima

IPC: G11C11/417 ,  G06F1/04 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/418 ,  H03K19/017 ,  H03K19/0185 ,  H03K19/096 ,  H03K5/135

CPC classification number: G11C11/4076 ,  G11C11/418 ,  H03K19/01735 ,  H03K19/01855

Abstract: A semiconductor circuit used as a buffer circuit having an input stage circuit for receiving an input clock signal and an inverted input clock signal, a bootstrap circuit including a transistor for receiving the output of the input stage circuit and for maintaining the gate voltage of the transistor at a high level during the standby period, and an output circuit, including a transistor which is switched on and off by the output of the bootstrap circuit, for generating an output clock signal; the semiconductor circuit further comprising a current leak circuit for maintaining, during the standby period, the voltage of a point in the semiconductor circuit which is charged during the standby period at the value corresponding to the voltage of the power source, whereby the delay of the output clock signal, caused of the fluctuation by the voltage of the power supply during the standby period, is improved and then the high speed access time in the dynamic memory is carried out.

Abstract translation: 一种用作缓冲电路的半导体电路，具有用于接收输入时钟信号和反相输入时钟信号的输入级电路，自举电路包括用于接收输入级电路的输出并保持晶体管的栅极电压的晶体管 在待机期间处于高电平;以及输出电路，包括由所述自举电路的输出接通和断开的晶体管，用于产生输出时钟信号; 所述半导体电路还包括电流泄漏电路，用于在所述待机期间保持所述半导体电路中在所述待机期间中以与所述电源的电压对应的值被充电的点的电压，由此所述延迟 在待机期间由电源的电压引起的输出时钟信号被提高，然后执行动态存储器中的高速访问时间。

公开(公告)号：US4511997A

公开(公告)日：1985-04-16

申请号：US439507

申请日：1982-11-05

Applicant: Shigeki Nozaki ,  Yoshihiro Takemae ,  Tomio Nakano

Inventor： Shigeki Nozaki ,  Yoshihiro Takemae ,  Tomio Nakano

IPC: G11C11/419 ,  G11C11/34 ,  G11C11/401 ,  G11C11/408 ,  G11C11/4096 ,  G11C11/40

CPC classification number: G11C11/4096

Abstract: A metal-insulator semiconductor dynamic memory device including sense amplifiers arrayed on a semiconductor substrate and divided into a plurality of sense amplifier groups. Column decoders are provided, one decoder for each sense amplifier group, each sense amplifier group being selected by the column decoder. One or more control signal lines for simultaneously selecting the output signals of at least two sense amplifiers in the sense amplifier group selected by the column decoder, a plurality of data buses for transferring the output signals of at least two sense amplifiers selected by one or more control signal lines, are included in the memory device. All of the sense amplifiers have the control signal lines and the data buses in common.

Abstract translation: 一种金属绝缘体半导体动态存储器件，包括排列在半导体衬底上并分成多个读出放大器组的读出放大器。 提供列解码器，每个读出放大器组的一个解码器，每个读出放大器组由列解码器选择。 一个或多个控制信号线，用于同时选择由列解码器选择的读出放大器组中的至少两个读出放大器的输出信号;多个数据总线，用于传送由一个或多个选择的至少两个读出放大器的输出信号 控制信号线被包括在存储器件中。 所有的读出放大器都具有控制信号线和数据总线。

公开(公告)号：US4771407A

公开(公告)日：1988-09-13

申请号：US79061

申请日：1987-07-29

Applicant: Yoshihiro Takemae ,  Shigeki Nozaki ,  Masao Nakano ,  Kimiaki Sato ,  Hatsuo Miyahara ,  Nobumi Kodama ,  Makoto Yanagisawa ,  Yasuhiro Takada ,  Satoshi Momozono

Inventor： Yoshihiro Takemae ,  Shigeki Nozaki ,  Masao Nakano ,  Kimiaki Sato ,  Hatsuo Miyahara ,  Nobumi Kodama ,  Makoto Yanagisawa ,  Yasuhiro Takada ,  Satoshi Momozono

IPC: H03K3/353 ,  G01R31/28 ,  G11C11/401 ,  G11C29/46 ,  G11C11/40

CPC classification number: G11C29/46

Abstract: In a semiconductor integrated circuit having first and second power supply lines for receiving a power supply voltage, an external input terminal for receiving an input signal, and a high voltage detection circuit for detecting at the external input terminal a high voltage higher than a predetermined voltage which is higher than the power supply voltage, the high voltage detection circuit comprises an input circuit connected to the external input terminal for generating circuit for generating a reference voltage; and a differential voltage amplifier connected to receive the detection voltage and the reference voltage for amplifying the difference between the detection voltage and the reference voltage, to thereby determine whether the high voltage is applied, the input circuit comprising; a level shift element connected to the external input terminal for providing the detection voltage; an impedance element connected between the level shift element and the second power supply line; and a leak current compensating element connected between the first power supply line and the level shift element for allowing a current to flow from the first power supply line through the leak current compensating element and the impedance element to the second power supply line when the high voltage is not applied to the external input terminal.

Abstract translation: 在具有用于接收电源电压的第一和第二电源线，用于接收输入信号的外部输入端子和用于在外部输入端子处检测高于预定电压的高电压的高电压检测电路的半导体集成电路中， 高电压检测电路包括连接到外部输入端的输入电路，用于产生用于产生参考电压的电路; 连接的差分电压放大器，用于接收检测电压和参考电压，用于放大检测电压和参考电压之间的差值，从而确定是否施加高电压，输入电路包括： 连接到所述外部输入端子以提供所述检测电压的电平移动元件; 连接在电平移位元件和第二电源线之间的阻抗元件; 以及泄漏电流补偿元件，其连接在所述第一电源线和所述电平移动元件之间，用于当高电压时允许电流从所述第一电源线流过所述漏电流补偿元件和所述阻抗元件流到所述第二电源线 不适用于外部输入端子。

公开(公告)号：US4583204A

公开(公告)日：1986-04-15

申请号：US452436

申请日：1982-12-23

Applicant: Yoshihiro Takemae ,  Shigeki Nozaki ,  Tsuyoshi Ohira

Inventor： Yoshihiro Takemae ,  Shigeki Nozaki ,  Tsuyoshi Ohira

IPC: G11C11/401 ,  G11C11/4072 ,  G11C11/409 ,  G11C11/417 ,  G11C11/24

CPC classification number: G11C11/4072

Abstract: A dynamic semiconductor memory device includes data output lines (D, D), a data output buffer (12), a column enable buffer (9), and an output enable buffer (11) for generating an output enable signal (OE) to enable the transmission of data from the data output lines to the data buffer. The output enable buffer is driven by the clock signals of the column enable buffer. An output disabling circuit (13) is provided to stop the generation of an output enable signal by the output enable buffer when the output enable buffer is not being driven by the column enable buffer. As a result, the data output buffer assumes a high-impedance state when a power supply is turned on.

Abstract translation: 动态半导体存储器件包括数据输出线（D，＆amp; upbar＆D），数据输出缓冲器（12），列使能缓冲器（9）和用于产生输出使能信号（OE）的输出使能信号 使数据从数据输出线传输到数据缓冲区。 输出使能缓冲器由列使能缓冲器的时钟信号驱动。 提供输出禁止电路（13），用于当输出使能缓冲器不被列使能缓冲器驱动时，通过输出使能缓冲器停止产生输出使能信号。 结果，当电源接通时，数据输出缓冲器呈现高阻抗状态。

公开(公告)号：US4550289A

公开(公告)日：1985-10-29

申请号：US453115

申请日：1982-12-27

Applicant: Katsuhiko Kabashima ,  Yoshihiro Takemae ,  Shigeki Nozaki ,  Tsuyoshi Ohira ,  Hatsuo Miyahara ,  Masakazu Kanai ,  Seiji Enomoto

Inventor： Katsuhiko Kabashima ,  Yoshihiro Takemae ,  Shigeki Nozaki ,  Tsuyoshi Ohira ,  Hatsuo Miyahara ,  Masakazu Kanai ,  Seiji Enomoto

IPC: G01R31/26 ,  G06F11/00 ,  H01L21/66 ,  H01L21/822 ,  H01L27/00 ,  H01L27/04 ,  G01R31/28

CPC classification number: G01R31/26 ,  G06F11/006

Abstract: A semiconductor integrated circuit (IC) device includes therein a test circuit. The test circuit operates to distinguish the power source level during the testing or ground level occurring at an internal node located inside the semiconductor chip. The test circuit includes a series-connected MIS transistor and an MIS diode. The gate of the MIS transistor is connected to the internal node. The MIS diode is connected to an external input/output (I/O) pin. The level at the internal node, i.e., the power source level or the ground level, can be distinguished by a first voltage level or a second voltage level applied to the external I/O pin, whichever enables a current to be drawn from the external I/O pin.

Abstract translation: 半导体集成电路（IC）装置包括测试电路。 测试电路用于在测试期间区分电源电平或在位于半导体芯片内部的内部节点处发生地电平。 测试电路包括串联连接的MIS晶体管和MIS二极管。 MIS晶体管的栅极连接到内部节点。 MIS二极管连接到外部输入/输出（I / O）引脚。 可以通过施加到外部I / O引脚的第一电压电平或第二电压电平来区分内部节点的电平，即电源电平或接地电平，无论哪一个使外部电流从外部 I / O引脚。

公开(公告)号：US4496850A

公开(公告)日：1985-01-29

申请号：US347465

申请日：1982-02-10

Applicant: Yoshihiro Takemae ,  Shigeki Nozaki ,  Katsuhiko Kabashima ,  Seiji Enomoto

Inventor： Yoshihiro Takemae ,  Shigeki Nozaki ,  Katsuhiko Kabashima ,  Seiji Enomoto

IPC: G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  H03K5/02 ,  H03K17/06 ,  H03K19/094 ,  H03K17/04 ,  H03K17/693 ,  H03K19/017

CPC classification number: G11C11/4085 ,  G11C11/4076 ,  H03K5/023

Abstract: A semiconductor circuit for driving a clock signal line comprising a first circuit for pulling up the potential of the clock signal line to the source voltage and a second circuit for pulling down the potential of the clock signal line to a lower voltage. A capacitor is connected to the clock signal line for receiving a potential push signal and pushing the potential of the clock signal line higher than the source voltage. The capacitor performs the function of capacitance only after the potential of the clock signal line is raised to the source voltage. The operational speed of a dynamic memory device associated with the semiconductor device is then enhanced.

Abstract translation: 一种用于驱动时钟信号线的半导体电路，包括用于将时钟信号线的电位提升到源极电压的第一电路和用于将时钟信号线的电位下拉到较低电压的第二电路。 电容器连接到时钟信号线，用于接收潜在的推送信号，并推动时钟信号线的电位高于源极电压。 只有在时钟信号线的电位升高到电源电压之后，电容才能执行电容。 然后增强与半导体器件相关联的动态存储器件的操作速度。

公开(公告)号：US4458337A

公开(公告)日：1984-07-03

申请号：US354498

申请日：1982-03-03

Applicant: Yoshihiro Takemae ,  Shigeki Nozaki ,  Tsutomu Mezawa ,  Katsuhiko Kabashima ,  Seiji Enomoto

Inventor： Yoshihiro Takemae ,  Shigeki Nozaki ,  Tsutomu Mezawa ,  Katsuhiko Kabashima ,  Seiji Enomoto

IPC: G11C11/413 ,  G11C11/408 ,  H03K3/356 ,  G11C13/00

CPC classification number: H03K3/356017 ,  H03K3/35606

Abstract: A buffer circuit comprises a flip-flop which is receives an external input via a first input circuit and a reference voltage via a second input circuit. Internal complementary outputs are then produced via an output circuit. The flip-flop cooperates with at least one level setting device by way of a second input circuit. The level setting device functions to produce a voltage level to deactivate the second input circuit during activation of the flip-flop.

Abstract translation: 缓冲电路包括经由第一输入电路接收外部输入的触发器和经由第二输入电路的参考电压。 然后通过输出电路产生内部互补输出。 触发器通过第二输入电路与至少一个电平设置装置协作。 电平设置装置用于产生电压电平，以在触发器激活期间停用第二输入电路。