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    METHOD OF MANUFACTURING PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE
    1.
    发明申请
    METHOD OF MANUFACTURING PHASE-CHANGE RANDOM ACCESS MEMORY DEVICE 审中-公开
    制造相变随机访问存储器件的方法

    公开(公告)号：US20130171798A1

    公开(公告)日：2013-07-04

    申请号：US13482190

    申请日：2012-05-29

    Applicant: Seung Beom BAEK ,  Hyung Suk Lee

    Inventor： Seung Beom BAEK ,  Hyung Suk Lee

    IPC: H01L21/02

    CPC classification number: H01L45/06 ,  H01L45/126 ,  H01L45/1608

    Abstract: A method of manufacturing a phase-change random access memory device. The method includes forming a word line on a semiconductor substrate, forming a switching element material and a hard mask material on the word line, etching the switching element material and the hard mask material to form a hole exposing the word line, forming an insulating material on a sidewall and a bottom of the hole, removing the hard mask material; and forming a heater material on the switching element material. The hard mask material has different etch selectivity from the insulating material.

    Abstract translation: 一种制造相变随机存取存储器件的方法。 该方法包括在半导体衬底上形成字线，在字线上形成开关元件材料和硬掩模材料，蚀刻开关元件材料和硬掩模材料以形成暴露字线的孔，形成绝缘材料 在孔的侧壁和底部上，去除硬掩模材料; 以及在所述开关元件材料上形成加热材料。 硬掩模材料与绝缘材料具有不同的蚀刻选择性。

    Semiconductor device having resistive device
    2.
    发明授权
    Semiconductor device having resistive device 有权
    具有电阻器件的半导体器件

    公开(公告)号：US08344346B2

    公开(公告)日：2013-01-01

    申请号：US13073521

    申请日：2011-03-28

    Applicant: Seung Beom Baek ,  Ja Chun Ku ,  Young Ho Lee ,  Jin Hyock Kim

    Inventor： Seung Beom Baek ,  Ja Chun Ku ,  Young Ho Lee ,  Jin Hyock Kim

    IPC: H01L29/02 ,  H01L29/06 ,  G11C11/00

    CPC classification number: H01L27/249 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146

    Abstract: A semiconductor memory device includes a plurality of word lines vertically formed on a surface of a semiconductor substrate, where each pair of the plurality of word lines form a set of word lines, a bit line formed parallel to the surface of the semiconductor substrate and disposed in plurality stacked between the word lines of each pair constituting the one set of word lines, and unit memory cells disposed between respective ones of the bit lines and an adjacent one of the pair of word lines of said one of the word line sets.

    Abstract translation: 半导体存储器件包括垂直形成在半导体衬底的表面上的多个字线，其中每对多条字线形成一组字线，平行于半导体衬底的表面形成的位线， 多个堆叠在构成所述一组字线的每一对的字线之间，以及设置在所述一个字线组中的所述位线中的相应位线与所述一对字线中的相邻一个之间的单元存储单元。

    SEMICONDUCTOR MANUFACTURING APPARATUS
    3.
    发明申请
    SEMICONDUCTOR MANUFACTURING APPARATUS 审中-公开
    半导体制造设备

    公开(公告)号：US20110107968A1

    公开(公告)日：2011-05-12

    申请号：US12674578

    申请日：2007-09-14

    Applicant: Taek Yong Jang ,  Byung Il Lee ,  Young Ho Lee ,  Seung Beom Baek

    Inventor： Taek Yong Jang ,  Byung Il Lee ,  Young Ho Lee ,  Seung Beom Baek

    IPC: C23C16/455 ,  C23C16/458 ,  C23C16/46

    CPC classification number: H01L21/68792 ,  C23C16/45521 ,  C23C16/4588 ,  C23C16/54 ,  C30B25/14 ,  C30B29/06 ,  H01L21/68721 ,  H01L21/68785

    Abstract: A semiconductor manufacturing apparatus includes: a reaction chamber for providing an airtight process space; a boat for loading/unloading a pair of semiconductor substrates into/from the reaction chamber, wherein the boat includes susceptors and rotary tables to be rotatably supported by a plurality of supporting rollers, each semiconductor substrate being mounted onto each susceptor and each susceptor being mounted onto each rotary table, respectively; heaters, arranged at backsides of the semiconductor substrates, for performing an epitaxial process in the reaction chamber; a process gas nozzle, installed to encircle an upper fringe of the semiconductor substrates; an exhaust gas nozzle, installed to encircle a lower fringe of the semiconductor substrates; and a purge gas nozzle for supplying a purge gas capable of preventing an outer wall of the process gas nozzle from being deposited, wherein the purge gas nozzle is arranged near to the process gas nozzle.

    Abstract translation: 半导体制造装置包括：用于提供气密处理空间的反应室; 用于将一对半导体基板装载到反应室中的船，其中，所述船包括由多个支撑辊可旋转地支撑的基座和旋转台，每个半导体基板安装在每个基座上，并且每个基座被安装 分别在每个旋转台上; 加热器，布置在半导体衬底的背面，用于在反应室中进行外延工艺; 工艺气体喷嘴，其安装成环绕半导体衬底的上边缘; 排气喷嘴，安装成环绕半导体衬底的下边缘; 以及用于供给能够防止工艺气体喷嘴的外壁的吹扫气体的吹扫气体喷嘴，其中吹扫气体喷嘴设置在工艺气体喷嘴附近。

    SEMICONDUCTOR DEVICE HAVING RESISTIVE DEVICE
    4.
    发明申请
    SEMICONDUCTOR DEVICE HAVING RESISTIVE DEVICE 有权
    具有电阻器件的半导体器件

    公开(公告)号：US20120153247A1

    公开(公告)日：2012-06-21

    申请号：US13073521

    申请日：2011-03-28

    Applicant: Seung Beom BAEK ,  Ja Chun Ku ,  Young Ho Lee ,  Jin Hyock Kim

    Inventor： Seung Beom BAEK ,  Ja Chun Ku ,  Young Ho Lee ,  Jin Hyock Kim

    IPC: H01L45/00

    CPC classification number: H01L27/249 ,  H01L27/2409 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1226 ,  H01L45/144 ,  H01L45/146

    Abstract: A semiconductor memory device includes a plurality of word lines vertically formed on a surface of a semiconductor substrate, where each pair of the plurality of word lines form a set of word lines, a bit line formed parallel to the surface of the semiconductor substrate and disposed in plurality stacked between the word lines of each pair constituting the one set of word lines, and unit memory cells disposed between respective ones of the bit lines and an adjacent one of the pair of word lines of said one of the word line sets.

    Abstract translation: 半导体存储器件包括垂直形成在半导体衬底的表面上的多个字线，其中每对多条字线形成一组字线，平行于半导体衬底的表面形成的位线， 多个堆叠在构成所述一组字线的每一对的字线之间，以及设置在所述一个字线组中的所述位线中的相应位线与所述一对字线中的相邻一个之间的单元存储单元。

    METHOD FOR MANUFACTURING SEMICONDUTOR DEVICE WITH STRAINED CHANNEL
    5.
    发明申请
    METHOD FOR MANUFACTURING SEMICONDUTOR DEVICE WITH STRAINED CHANNEL 审中-公开
    制造具有应变通道的半导体器件的方法

    公开(公告)号：US20110003450A1

    公开(公告)日：2011-01-06

    申请号：US12646207

    申请日：2009-12-23

    Applicant: Young-Ho LEE ,  Tae-Hang Ahn ,  Seung-Beom Baek ,  Jun-Hee Cho ,  Jeong-Seon Kim

    Inventor： Young-Ho LEE ,  Tae-Hang Ahn ,  Seung-Beom Baek ,  Jun-Hee Cho ,  Jeong-Seon Kim

    IPC: H01L21/336

    CPC classification number: H01L29/66636 ,  H01L29/165 ,  H01L29/6653 ,  H01L29/78 ,  H01L29/7848

    Abstract: A method for forming a semiconductor device includes forming a gate pattern over a silicon substrate, forming gate spacers over both sidewalls of the gate pattern, forming a dummy gate spacer over a sidewall of each one of the gate spacers, forming a recess region having inclined sidewalls extending in a direction to a channel region under the gate pattern by recess-etching the silicon substrate, filling the recess region with an epitaxial film, which becomes a source region or a drain region, through a selective epitaxial growth process, and removing the dummy gate spacer.

    Abstract translation: 一种用于形成半导体器件的方法包括在硅衬底上形成栅极图案，在栅极图案的两个侧壁上形成栅极间隔物，在每个栅极间隔物的侧壁上形成虚拟栅极隔离物，形成具有倾斜 通过凹槽蚀刻硅衬底沿着栅极图案下方的沟道区域的方向延伸的侧壁，通过选择性外延生长工艺用成为源极区域或漏极区域的外延膜填充凹部区域， 虚拟栅极隔板。

    PLASMA DOPING METHOD AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME
    8.
    发明申请
    PLASMA DOPING METHOD AND METHOD FOR FABRICATING SEMICONDUCTOR DEVICE USING THE SAME 审中-公开
    等离子喷涂方法和使用其制造半导体器件的方法

    公开(公告)号：US20110189843A1

    公开(公告)日：2011-08-04

    申请号：US12774311

    申请日：2010-05-05

    Applicant: Jin-Ku Lee ,  Jae-Geun Oh ,  Young-Ho Lee ,  Mi-Ri Lee ,  Seung-Beom Baek

    Inventor： Jin-Ku Lee ,  Jae-Geun Oh ,  Young-Ho Lee ,  Mi-Ri Lee ,  Seung-Beom Baek

    IPC: H01L21/306

    CPC classification number: H01L29/66575 ,  H01L21/306

    Abstract: A doping method that forms a doped region at a desired location of a three-dimensional (3D) conductive structure, controls the doping depth and doping dose of the doped region relatively easily, has a shallow doping depth, and prevents a floating body effect. A semiconductor device is fabricated using the same doping method. The method includes, forming a conductive structure having a sidewall, exposing a portion of the sidewall of the conductive structure, and forming a doped region in the exposed portion of the sidewall by performing a plasma doping process.

    Abstract translation: 在三维（3D）导电结构的期望位置处形成掺杂区域的掺杂方法相对容易地控制掺杂深度和掺杂区域的掺杂剂量，具有浅掺杂深度，并且防止浮体效应。 使用相同的掺杂方法制造半导体器件。 该方法包括：形成具有侧壁的导电结构，暴露导电结构的侧壁的一部分，以及通过执行等离子体掺杂工艺在侧壁的暴露部分中形成掺杂区域。

    Schottky diode, resistive memory device having schottky diode and method of manufacturing the same
    9.
    发明授权
    Schottky diode, resistive memory device having schottky diode and method of manufacturing the same 失效
    肖特基二极管，具有肖特基二极管的电阻式存储器件及其制造方法

    公开(公告)号：US08541775B2

    公开(公告)日：2013-09-24

    申请号：US13331698

    申请日：2011-12-20

    Applicant: Seung Beom Baek ,  Young Ho Lee ,  Jin Ku Lee ,  Mi Ri Lee

    Inventor： Seung Beom Baek ,  Young Ho Lee ,  Jin Ku Lee ,  Mi Ri Lee

    IPC: H01L21/02

    CPC classification number: H01L27/101 ,  H01L27/1021 ,  H01L27/2409 ,  H01L29/872 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/1683

    Abstract: A schottky diode, a resistive memory device including the schottky diode and a method of manufacturing the same. The resistive memory device includes a semiconductor substrate including a word line, a schottky diode formed on the word line, and a storage layer formed on the schottky diode. The schottky diode includes a first semiconductor layer, a conductive layer formed on the first semiconductor layer and having a lower work function than the first semiconductor layer, and a second semiconductor layer formed on the to conductive layer.

    Abstract translation: 肖特基二极管，包括肖特基二极管的电阻式存储器件及其制造方法。 电阻式存储器件包括一个包括字线，形成在字线上的肖特基二极管和形成在肖特基二极管上的存储层的半导体衬底。 肖特基二极管包括第一半导体层，形成在第一半导体层上并具有比第一半导体层低的功函数的导电层和形成在导电层上的第二半导体层。

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