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    METHOD FOR FORMING DEVICE ISOLATION LAYER OF SEMICONDUCTOR DEVICE AND NON-VOLATILE MEMORY DEVICE
    3.
    发明申请
    METHOD FOR FORMING DEVICE ISOLATION LAYER OF SEMICONDUCTOR DEVICE AND NON-VOLATILE MEMORY DEVICE 有权
    形成半导体器件和非易失性存储器件的器件隔离层的方法

    公开(公告)号：US20100167496A1

    公开(公告)日：2010-07-01

    申请号：US12473307

    申请日：2009-05-28

    申请人： Jae-Hyoung Koo ,  Jin-Woong Kim ,  Mi-Ri Lee ,  Chi-Ho Kim ,  Jin-Ho Bin

    发明人： Jae-Hyoung Koo ,  Jin-Woong Kim ,  Mi-Ri Lee ,  Chi-Ho Kim ,  Jin-Ho Bin

    IPC分类号： H01L21/762

    CPC分类号： H01L21/76232 ,  H01L27/11521 ,  H01L27/11568

    摘要： A method for forming a device isolation layer of a semiconductor device or a non-volatile memory device is provided. A method for forming a device isolation layer of a semiconductor device includes: forming trenches having a first predetermined depth by etching a substrate; forming a first insulation layer having a second predetermined depth inside the trenches; forming a liner oxide layer having a predetermined thickness on internal walls of the trenches with the first insulation layer formed therein; and forming a second insulation layer for forming a device isolation layer over the substrate with the liner oxide layer formed therein, wherein the second insulation layer has a lower etch rate than that of the first insulation layer.

    摘要翻译： 提供了一种用于形成半导体器件或非易失性存储器件的器件隔离层的方法。 一种用于形成半导体器件的器件隔离层的方法包括：通过蚀刻衬底来形成具有第一预定深度的沟槽; 形成在所述沟槽内具有第二预定深度的第一绝缘层; 在其中形成有第一绝缘层的沟槽的内壁上形成具有预定厚度的衬里氧化物层; 以及形成用于在其上形成有衬里氧化物层的衬底上形成器件隔离层的第二绝缘层，其中所述第二绝缘层具有比所述第一绝缘层的蚀刻速率更低的蚀刻速率。

    Method of Manufacturing Semiconductor Device using Salicide Process
    5.
    发明申请
    Method of Manufacturing Semiconductor Device using Salicide Process 失效
    使用杀菌剂工艺制造半导体器件的方法

    公开(公告)号：US20090186456A1

    公开(公告)日：2009-07-23

    申请号：US12346011

    申请日：2008-12-30

    申请人： Young Jin Lee ,  Dong Sun Sheen ,  Seok Pyo Song ,  Mi Ri Lee ,  Chi Ho Kim ,  Gil Jae Park ,  Bo Min Seo

    发明人： Young Jin Lee ,  Dong Sun Sheen ,  Seok Pyo Song ,  Mi Ri Lee ,  Chi Ho Kim ,  Gil Jae Park ,  Bo Min Seo

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823814 ,  H01L21/823425 ,  H01L21/823835

    摘要： A method for manufacturing a semiconductor device using a salicide process, which includes forming a gate dielectric layer over a silicon substrate including a PMOS region and an NMOS region; forming a first silicon pattern in the NMOS region and a second silicon pattern in the PMOS region; forming a first metal layer that is in contact with the first silicon pattern and the exposed first portion of the silicon substrate; and forming a first gate, a first junction, a second gate, and a second junction by performing a heat treatment to silicify the respective first and second silicon patterns and the silicon substrate.

    摘要翻译： 一种使用自对准硅化物工艺制造半导体器件的方法，包括在包括PMOS区域和NMOS区域的硅衬底上形成栅极电介质层; 在所述NMOS区域中形成第一硅图案和在所述PMOS区域中形成第二硅图案; 形成与所述第一硅图案和所述暴露的所述硅衬底的第一部分接触的第一金属层; 以及通过进行热处理以使相应的第一和第二硅图案和硅衬底硅化而形成第一栅极，第一结，第二栅极和第二结。

    MP3 player
    7.
    外观设计
    MP3 player 有权

    公开(公告)号：USD550712S1

    公开(公告)日：2007-09-11

    申请号：US29264117

    申请日：2006-08-04

    申请人： Mi-Ri Lee

    设计人： Mi-Ri Lee

    SEMICONDUCTOR DEVICE WITH ONE-SIDE-CONTACT AND METHOD FOR FABRICATING THE SAME
    9.
    发明申请
    SEMICONDUCTOR DEVICE WITH ONE-SIDE-CONTACT AND METHOD FOR FABRICATING THE SAME 有权
    具有单面接触的半导体器件及其制造方法

    公开(公告)号：US20110073940A1

    公开(公告)日：2011-03-31

    申请号：US12649999

    申请日：2009-12-30

    申请人： Jin-Ku LEE ,  Young-Ho Lee ,  Mi-Ri Lee

    发明人： Jin-Ku LEE ,  Young-Ho Lee ,  Mi-Ri Lee

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7845 ,  H01L21/28518 ,  H01L27/10876 ,  H01L27/10885 ,  H01L27/10888 ,  H01L29/41791 ,  H01L29/42356 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7856

    摘要： A method for fabricating a semiconductor device includes forming a first conductive layer doped with an impurity for forming a cell junction over a semiconductor substrate, forming a second conductive layer over the first conductive layer, forming a plurality of active regions by etching the second conductive layer and the first conductive layer, the plurality of the active regions being separated from one another by trenches, forming a side contact connected to a sidewall of the first conductive layer, and forming a plurality of metal bit lines each connected to the side contact and filling a portion of each trench.

    摘要翻译： 一种制造半导体器件的方法包括：在半导体衬底上形成掺杂有用于形成电池结的杂质的第一导电层，在第一导电层上形成第二导电层，通过蚀刻第二导电层形成多个有源区 和所述第一导电层，所述多个有源区域通过沟槽彼此分开，形成连接到所述第一导电层的侧壁的侧面接触，以及形成多个金属位线，每个金属位线连接到所述侧面接触和填充 每个沟槽的一部分。

    Method of fabricating a non-volatile memory device
    10.
    发明授权
    Method of fabricating a non-volatile memory device 失效
    制造非易失性存储器件的方法

    公开(公告)号：US07585730B1

    公开(公告)日：2009-09-08

    申请号：US12164721

    申请日：2008-06-30

    申请人： Seok Pyo Song ,  Dong Sun Sheen ,  Young Jin Lee ,  Mi Ri Lee ,  Chi Ho Kim ,  Gil Jae Park ,  Bo Min Seo

    发明人： Seok Pyo Song ,  Dong Sun Sheen ,  Young Jin Lee ,  Mi Ri Lee ,  Chi Ho Kim ,  Gil Jae Park ,  Bo Min Seo

    IPC分类号： H01L21/8247

    CPC分类号： H01L29/7881 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42324

    摘要： A method of fabricating a non-volatile memory device includes forming a tunneling layer and a conductive layer on a semiconductor substrate, and patterning the conductive layer, the tunneling layer, and the semiconductor substrate to form a conductive pattern, a tunneling pattern, and a trench in the semiconductor substrate. The method also includes filling the trench with a insulating material, and exposing a partial sidewall of the conductive pattern. The method further includes recessing the exposed partial sidewall of the conductive pattern in an inward direction to form a floating gate. The floating gate includes a base portion and a protruding portion having a width smaller than that of the base portion. The method also includes etching the insulating layer to form an isolation layer that exposes the base portion of the floating gate. Still further, the method includes forming a dielectric layer, that extends along the base and protruding portions of the floating gate, and a control gate that covers the base and protruding portions of the floating gate.

    摘要翻译： 一种制造非易失性存储器件的方法包括在半导体衬底上形成隧道层和导电层，并且对导电层，隧道层和半导体衬底进行构图以形成导电图案，隧道图案和 沟槽在半导体衬底中。 该方法还包括用绝缘材料填充沟槽，以及暴露导电图案的部分侧壁。 该方法还包括将导电图案的暴露部分侧壁向内凹入以形成浮动栅极。 浮动门包括基部和具有小于基部的宽度的突出部分。 该方法还包括蚀刻绝缘层以形成暴露浮动栅极的基部的隔离层。 此外，该方法包括形成沿着基极延伸的电介质层和浮动栅极的突出部分，以及覆盖浮动栅极的基部和突出部分的控制栅极。