Patent search ap:"Sarah E. Kim" Page 1

1.

发明授权
Microelectronic assembly having thermoelectric elements to cool a die and a method of making the same 有权

公开(公告)号：US07537954B2

公开(公告)日：2009-05-26

申请号：US11298280

申请日：2005-12-09

Applicant: Shriram Ramanathan , Sarah E. Kim , R. Scott List , Gregory M. Chrysler

Inventor： Shriram Ramanathan , Sarah E. Kim , R. Scott List , Gregory M. Chrysler

IPC: H01L27/16 , H01L21/70

CPC classification number: H01L35/32 , H01L23/38 , H01L23/50 , H01L24/11 , H01L24/13 , H01L24/48 , H01L24/73 , H01L24/81 , H01L27/16 , H01L2224/05001 , H01L2224/13099 , H01L2224/16145 , H01L2224/451 , H01L2224/48091 , H01L2224/48471 , H01L2224/73253 , H01L2224/73257 , H01L2224/81801 , H01L2924/0001 , H01L2924/00014 , H01L2924/01005 , H01L2924/01015 , H01L2924/01032 , H01L2924/01033 , H01L2924/01051 , H01L2924/01052 , H01L2924/01075 , H01L2924/01078 , H01L2924/01082 , H01L2924/14 , H01L2924/15312 , H01L2924/19041 , H01L2924/19043 , H01L2924/00 , H01L2224/45099 , H01L2224/05599 , H01L2224/4554

Abstract: A microelectronic assembly is provided, having thermoelectric elements formed on a die so as to pump heat away from the die when current flows through the thermoelectric elements. In one embodiment, the thermoelectric elements are integrated between conductive interconnection elements on an active side of the die. In another embodiment, the thermoelectric elements are on a backside of the die and electrically connected to a carrier substrate on a front side of the die. In a further embodiment, the thermoelectric elements are formed on a secondary substrate and transferred to the die.

2.

发明授权
Method and apparatus for low temperature copper to copper bonding 有权
Title translation: 低温铜铜键合的方法和装置

公开(公告)号：US07183648B2

公开(公告)日：2007-02-27

申请号：US10861030

申请日：2004-06-04

Applicant: Shriram Ramanathan , Sarah E. Kim

Inventor： Shriram Ramanathan , Sarah E. Kim

IPC: H01L23/48 , H01L23/52 , H01L29/40 , B23K31/00

CPC classification number: H01L24/16 , H01L24/11 , H01L24/12 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/13099 , H01L2224/13124 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/812 , H01L2224/81801 , H01L2224/81894 , H01L2224/8383 , H01L2224/9202 , H01L2225/06513 , H01L2924/01005 , H01L2924/01006 , H01L2924/01012 , H01L2924/01013 , H01L2924/01022 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01044 , H01L2924/01045 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01073 , H01L2924/01075 , H01L2924/01076 , H01L2924/01077 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/14 , H01L2924/19041 , H01L2924/00014

Abstract: A method comprising: coating a conductive bump on a first substrate with a conductive material to form a coated conductive bump; coating a conductive bump on a second substrate with a conductive material to form a coated conductive bump; and bonding the coated conductive bump on the first substrate to the coated conductive bump on the second substrate to electrically connect the first substrate to the second substrate.

Abstract translation: 一种方法，包括：用导电材料涂覆在第一基板上的导电凸块以形成涂覆的导电凸块; 用导电材料在第二基板上涂覆导电凸块以形成涂覆的导电凸块; 以及将所述第一基板上的涂覆的导电凸块接合到所述第二基板上的涂覆的导电凸块上，以将所述第一基板电连接到所述第二基板。

3.

发明授权
Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices 有权
Title translation: 垂直堆叠支持不同有源集成电路（IC）器件的多个晶片的工艺

公开(公告)号：US07157787B2

公开(公告)日：2007-01-02

申请号：US10855032

申请日：2004-05-26

Applicant: Sarah E. Kim , R. Scott List , Scot A. Kellar

Inventor： Sarah E. Kim , R. Scott List , Scot A. Kellar

IPC: H01L29/40 , H01L23/02 , H01L23/48 , H01L23/52

CPC classification number: H01L21/76831 , H01L21/76804 , H01L21/76807 , H01L21/76898 , H01L23/544 , H01L25/0657 , H01L25/50 , H01L2223/54426 , H01L2223/54473 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/8083 , H01L2224/80895 , H01L2224/81894 , H01L2224/94 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06589 , H01L2924/0002 , H01L2924/01079 , H01L2924/13091 , H01L2224/05552 , H01L2224/81 , H01L2224/83

Abstract: A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, to establish electrical connections between active devices on vertically stacked wafers; and forming one or more vias to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect. Metal bonding areas on opposing surfaces of the adjacent wafers can be increased by using one or more dummy vias, tapered vias, or incorporating an existing copper (Cu) dual damascene process.

Abstract translation: 提供垂直堆叠晶片的方法以形成三维（3D）晶片堆叠。这种方法包括：在相邻晶片的相对表面上选择性地沉积多条金属线; 通过金属线接合相邻的晶片，以在垂直堆叠的晶片上的有源器件之间建立电连接; 以及形成一个或多个通孔以在垂直堆叠的晶片上的有源器件和外部互连之间建立电连接。通过使用一个或多个虚拟通孔，锥形通孔或并入现有的铜（Cu）双镶嵌工艺，可以增加相邻晶片的相对表面上的金属结合区域。

4.

发明授权
Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack 有权

公开(公告)号：US07148565B2

公开(公告)日：2006-12-12

申请号：US10443831

申请日：2003-05-23

Applicant: Sarah E. Kim , R. Scott List , Tom Letson

Inventor： Sarah E. Kim , R. Scott List , Tom Letson

IPC: H01L23/04 , H01L23/02

CPC classification number: H01L21/30604 , H01L21/3065 , H01L21/76898 , H01L23/481 , H01L23/66 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/81193 , H01L2224/81201 , H01L2224/81801 , H01L2224/8182 , H01L2225/06513 , H01L2225/06541 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/13091 , H01L2924/14 , H01L2924/30107

Abstract: A method of forming a silicon (Si) via in vertically stacked wafers is provided with a contact plug extending from selected metallic lines of a top wafer and an etch stop layer formed prior to the contact plug. Such a method comprises selectively etching through the silicon (Si) of the top wafer until stopped by the etch stop layer to form the Si via; depositing an oxide layer to insulate a sidewall of the Si via; forming a barrier layer on the oxide layer and on the bottom of the Si via; and depositing a conduction metal into the Si via to provide electrical connection between active IC devices located on vertically stacked wafers and an external interconnect.

5.

发明授权
Ultra-high capacitance device based on nanostructures 有权
Title translation: 基于纳米结构的超高电容器件

公开(公告)号：US06911373B2

公开(公告)日：2005-06-28

申请号：US10251197

申请日：2002-09-20

Applicant: Scot A. Kellar , Sarah E. Kim

Inventor： Scot A. Kellar , Sarah E. Kim

IPC: G11C13/02 , H01G4/008 , H01G4/33 , H01L21/02 , H01L21/8242 , H01L27/08 , H01L21/20

CPC classification number: H01L28/84 , B82Y10/00 , G11C13/0033 , G11C13/025 , G11C2213/16 , G11C2213/81 , H01G4/008 , H01G4/33 , H01L27/0805 , H01L27/1085 , Y10S977/70 , Y10S977/72 , Y10S977/721 , Y10S977/723 , Y10S977/902 , Y10S977/963 , Y10T428/24802

Abstract: The present invention discloses a method including providing a substrate; forming a lower conductor over the substrate; forming a conducting nanostructure over the lower conductor; forming a thin dielectric over the conducting nanostructure; and forming an upper conductor over the thin dielectric.The present invention further discloses a device including a substrate; a lower conductor located over the substrate; a conducting nanostructure located over the lower conductor; a thin dielectric located over the conducting nanostructure; and an upper conductor located over the thin dielectric.

Abstract translation: 本发明公开了一种提供基板的方法，在衬底上形成下导体; 在下导体上形成导电纳米结构; 在导电纳米结构上形成薄的电介质; 以及在所述薄电介质上形成上导体。本发明还公开了一种包括基板的装置; 位于衬底上方的下导体; 位于下导体上的导电纳米结构; 位于导电纳米结构之上的薄电介质; 以及位于薄电介质上方的上导体。

6.

发明授权
Fabrication of 3-D capacitor with dual damascene process 有权
Title translation: 具有双镶嵌工艺的三维电容器的制造

公开(公告)号：US06790780B2

公开(公告)日：2004-09-14

申请号：US09965972

申请日：2001-09-27

Applicant: Sarah E. Kim , R. Scott List , Bruce A. Block

Inventor： Sarah E. Kim , R. Scott List , Bruce A. Block

IPC: H01L21302

CPC classification number: H01L21/311 , H01L21/302 , H01L21/76807 , H01L21/76877 , H01L28/55 , H01L28/75

Abstract: A three dimensional capacitor fabricated as part of a dual damascene process is disclosed. The capacitor structure comprises two barrier metal layers separated by a high k dielectric and is formed in all the via and trench openings. The upper barrier layer and dielectric is selectively removed from those openings which will have ordinary vias and conductors, the other opening remains as capaitor.

Abstract translation: 公开了作为双镶嵌工艺的一部分制造的三维电容器。电容器结构包括由高k电介质隔开的两个阻挡金属层，并且形成在所有通孔和沟槽开口中。从具有普通通孔和导体的那些开口选择性地去除上阻挡层和电介质，另一个开口保持为电容器。

7.

发明授权
Process of vertically stacking multiple wafers supporting different active integrated circuit (IC) devices 有权

公开(公告)号：US06762076B2

公开(公告)日：2004-07-13

申请号：US10077967

申请日：2002-02-20

Applicant: Sarah E. Kim , R. Scott List , Scot A. Kellar

Inventor： Sarah E. Kim , R. Scott List , Scot A. Kellar

IPC: H01L2144

CPC classification number: H01L21/76831 , H01L21/76804 , H01L21/76807 , H01L21/76898 , H01L23/544 , H01L25/0657 , H01L25/50 , H01L2223/54426 , H01L2223/54473 , H01L2224/0401 , H01L2224/0557 , H01L2224/13025 , H01L2224/8083 , H01L2224/80895 , H01L2224/81894 , H01L2224/94 , H01L2225/06513 , H01L2225/06524 , H01L2225/06541 , H01L2225/06589 , H01L2924/0002 , H01L2924/01079 , H01L2924/13091 , H01L2224/05552 , H01L2224/81 , H01L2224/83

Abstract: A method of vertically stacking wafers is provided to form three-dimensional (3D) wafer stack. Such method comprising: selectively depositing a plurality of metallic lines on opposing surfaces of adjacent wafers; bonding the adjacent wafers, via the metallic lines, to establish electrical connections between active devices on vertically stacked wafers; and forming one or more vias to establish electrical connections between the active devices on the vertically stacked wafers and an external interconnect. Metal bonding areas on opposing surfaces of the adjacent wafers can be increased by using one or more dummy vias, tapered vias, or incorporating an existing copper (Cu) dual damascene process.

8.

发明授权
Etch stop layer for silicon (Si) via etch in three-dimensional (3-D) wafer-to-wafer vertical stack 有权

公开(公告)号：US06645832B2

公开(公告)日：2003-11-11

申请号：US10077822

申请日：2002-02-20

Applicant: Sarah E. Kim , R. Scott List , Tom Letson

Inventor： Sarah E. Kim , R. Scott List , Tom Letson

IPC: H01L2144

CPC classification number: H01L21/30604 , H01L21/3065 , H01L21/76898 , H01L23/481 , H01L23/66 , H01L24/81 , H01L25/0657 , H01L25/50 , H01L2224/13139 , H01L2224/13144 , H01L2224/13147 , H01L2224/81193 , H01L2224/81201 , H01L2224/81801 , H01L2224/8182 , H01L2225/06513 , H01L2225/06541 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/01049 , H01L2924/0105 , H01L2924/01073 , H01L2924/01074 , H01L2924/01079 , H01L2924/01082 , H01L2924/13091 , H01L2924/14 , H01L2924/30107

Abstract: A method of forming a silicon (Si) via in vertically stacked wafers is provided with a contact plug extending from selected metallic lines of a top wafer and an etch stop layer formed prior to the contact plug. Such a method comprises selectively etching through the silicon (Si) of the top wafer until stopped by the etch stop layer to form the Si via; depositing an oxide layer to insulate a sidewall of the Si via; forming a barrier layer on the oxide layer and on the bottom of the Si via; and depositing a conduction metal into the Si via to provide electrical connection between active IC devices located on vertically stacked wafers and an external interconnect.