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    Process for Enhanced 3D Integration and Structures Generated using the Same
    8.
    发明申请
    Process for Enhanced 3D Integration and Structures Generated using the Same 有权
    增强型3D集成和使用其生成的结构的过程

    公开(公告)号：US20120307444A1

    公开(公告)日：2012-12-06

    申请号：US13586054

    申请日：2012-08-15

    申请人： Evan G. Colgan ,  Sampath Purushothaman ,  Roy R. Yu

    发明人： Evan G. Colgan ,  Sampath Purushothaman ,  Roy R. Yu

    IPC分类号： H05K1/14 ,  H05K1/11 ,  G06F1/16

    CPC分类号： H01L23/49816 ,  B23P11/00 ,  H01L21/78 ,  H01L2924/0002 ,  H05K1/11 ,  H05K1/14 ,  H05K7/00 ,  Y10T29/49826 ,  H01L2924/00

    摘要： An enhanced 3D integration structure comprises a logic microprocessor chip bonded to a collection of vertically stacked memory slices and an optional set of outer vertical slices comprising optoelectronic devices. Such a device enables both high memory content in close proximity to the logic circuits and a high bandwidth for logic to memory communication. Additionally, the provision of optoelectronic devices in the outer slices of the vertical slice stack enables high bandwidth direct communication between logic processor chips on adjacent enhanced 3D modules mounted next to each other or on adjacent packaging substrates. A method to fabricate such structures comprises using a template assembly which enables wafer format processing of vertical slice stacks.

    摘要翻译： 增强的3D集成结构包括结合到垂直堆叠的存储器片的集合的逻辑微处理器芯片和包括光电子器件的可选的一组外部垂直片。 这样一种装置使得能够靠近逻辑电路的高存储器内容和用于逻辑到存储器通信的高带宽。 此外，在垂直切片堆叠的外切片中提供光电子器件可实现彼此相邻或相邻封装衬底上安装的相邻增强型3D模块之间的逻辑处理器芯片之间的高带宽直接通信。 制造这种结构的方法包括使用能够对垂直切片堆叠进行晶片格式处理的模板组件。

    DUAL DAMASCENE PROCESSING FOR GATE CONDUCTOR AND ACTIVE AREA TO FIRST METAL LEVEL INTERCONNECT STRUCTURES
    10.
    发明申请
    DUAL DAMASCENE PROCESSING FOR GATE CONDUCTOR AND ACTIVE AREA TO FIRST METAL LEVEL INTERCONNECT STRUCTURES 审中-公开
    门控导体和主动区域的双重加工处理与第一金属层间互连结构

    公开(公告)号：US20100308380A1

    公开(公告)日：2010-12-09

    申请号：US12478850

    申请日：2009-06-05

    申请人： Mary Beth Rothwell ,  Roy R. Yu

    发明人： Mary Beth Rothwell ,  Roy R. Yu

    IPC分类号： H01L23/48 ,  H01L21/768 ,  H01L29/78

    CPC分类号： H01L21/76895 ,  H01L21/76807 ,  H01L21/76816 ,  H01L23/485 ,  H01L23/53266 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A method of forming a semiconductor device includes forming a first interlevel dielectric (ILD) layer over one or more transistor structures formed on a substrate, the one or more transistor structures including an active area, source/drain contact and a gate conductor formed over the substrate; forming a first metal (M1) level trench in an upper portion of the first ILD layer, followed by forming vias in a lower portion of the first ILD layer, down to the source/drain contact and down to the gate conductor; and filling both the trench and vias with a conductive material, thereby resulting in a dual damascene metal process at and below the M1 level of the semiconductor device.

    摘要翻译： 形成半导体器件的方法包括在形成在衬底上的一个或多个晶体管结构上形成第一层间电介质（ILD）层，所述一个或多个晶体管结构包括有源区，源极/漏极接触和栅极导体， 基质; 在第一ILD层的上部形成第一金属（M1）电平沟槽，随后在第一ILD层的下部形成通孔，向下到源极/漏极接触并向下到栅极导体; 并且用导电材料填充沟槽和通孔，从而导致在半导体器件的M1电平以下的双镶嵌金属工艺。