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    Method of operating a memory system having an erase control unit
    2.
    发明授权
    Method of operating a memory system having an erase control unit 有权
    一种具有擦除控制单元的存储系统的操作方法

    公开(公告)号：US09437310B2

    公开(公告)日：2016-09-06

    申请号：US14827930

    申请日：2015-08-17

    申请人： Eun Chu Oh ,  Hong Rak Son ,  Junjin Kong

    发明人： Eun Chu Oh ,  Hong Rak Son ,  Junjin Kong

    IPC分类号： G11C16/10 ,  G11C16/16 ,  G11C11/56 ,  G11C16/34 ,  G11C16/26

    CPC分类号： G11C16/16 ,  G11C11/5635 ,  G11C16/26 ,  G11C16/3468

    摘要： A method of operating a memory system including a nonvolatile memory including a memory block, and a memory controller including an erase control unit, includes performing pre-reading a plurality of memory cells connected to a selected word line of the memory block, generating an off cell count based on the pre-reading result, by operation of the erase control unit, comparing the off cell count with a reference value to generate a comparison result, and changing an erase operation condition based on the comparison result, by operation of the nonvolatile memory, and erasing the memory block according to the changed erase operation condition.

    摘要翻译： 一种操作包括包括存储器块的非易失性存储器的存储器系统的方法和包括擦除控制单元的存储器控​​制器，包括执行预读取连接到所述存储器块的选定字线的多个存储器单元，产生关断 基于预读取结果的单元计数，通过擦除控制单元的操作，将关闭单元计数与参考值进行比较以产生比较结果，以及通过非易失性存储器的操作来改变基于比较结果的擦除操作条件 存储器，并根据改变的擦除操作条件擦除存储器块。

    SEMICONDUCTOR MEMORY SYSTEMS USING REGRESSION ANALYSIS AND READ METHODS THEREOF
    3.
    发明申请
    SEMICONDUCTOR MEMORY SYSTEMS USING REGRESSION ANALYSIS AND READ METHODS THEREOF 审中-公开
    使用回归分析的半导体存储器系统及其读取方法

    公开(公告)号：US20150332778A1

    公开(公告)日：2015-11-19

    申请号：US14811222

    申请日：2015-07-28

    申请人： Kwanghoon KIM ,  Junjin KONG ,  Changkyu SEOL ,  Hong Rak SON

    发明人： Kwanghoon KIM ,  Junjin KONG ,  Changkyu SEOL ,  Hong Rak SON

    IPC分类号： G11C16/26

    CPC分类号： G11C16/26 ,  G11C11/5642 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3422 ,  G11C16/349

    摘要： A memory system includes: a bit counter and a regression analyzer. The bit counter is configured to generate a plurality of count values based on data read from selected memory cells using a plurality of different read voltages, each of the plurality of count values being indicative of a number of memory cells of a memory device having threshold voltages between pairs of the plurality of different read voltages. The regression analyzer is configured to determine read voltage for the selected memory cells based on the plurality of count values using regression analysis.

    摘要翻译： 存储器系统包括：位计数器和回归分析器。 位计数器被配置为基于使用多个不同的读取电压从所选择的存储器单元读取的数据生成多个计数值，多个计数值中的每一个表示具有阈值电压的存储器件的存储单元的数量 在多个不同读取电压的对之间。 回归分析器被配置为使用回归分析来基于多个计数值来确定所选择的存储器单元的读取电压。

    Non-volatile random access memory device and data read method thereof
    5.
    发明授权
    Non-volatile random access memory device and data read method thereof 有权
    非易失性随机存取存储器件及其数据读取方法

    公开(公告)号：US09093145B2

    公开(公告)日：2015-07-28

    申请号：US14141609

    申请日：2013-12-27

    申请人： Eun Chu Oh ,  JunJin Kong ,  Hong Rak Son ,  Younggeon Yoo

    发明人： Eun Chu Oh ,  JunJin Kong ,  Hong Rak Son ,  Younggeon Yoo

    IPC分类号： G11C7/00 ,  G11C13/00

    CPC分类号： G11C13/004 ,  G11C11/16 ,  G11C11/1673 ,  G11C13/0002 ,  G11C13/0004 ,  G11C2013/0054

    摘要： A nonvolatile random access memory device includes a plurality of memory cells configured to store data therein, a plurality of reference cells separate from the memory cells, the reference cells each configured to output a corresponding reference cell signal, and a read/write circuit. The read/write circuit is configured to generate from the reference cell signals a reference signal which is variable to have a plurality of different reference levels. The read/write circuit is further configured to identify, in response to the reference signal, a logic state among a first logic state and a second logic state for each of one or more selected memory cells, and to output read data corresponding to the identified logic state.

    摘要翻译： 非易失性随机存取存储器件包括多个存储器单元，其被配置为在其中存储数据，多个参考单元与存储器单元分离，每个参考单元被配置为输出相应的参考单元信号，以及读/写电路。 读/写电路被配置为从参考单元信号产生可变为具有多个不同参考电平的参考信号。 读/写电路还被配置为响应于参考信号识别一个或多个所选择的存储器单元中的每一个的第一逻辑状态和第二逻辑状态之间的逻辑状态，并且输出与所识别的对应的读取数据 逻辑状态。

    NONVOLATILE MEMORY DEVICE AND SUB-BLOCK MANAGING METHOD THEREOF
    6.
    发明申请
    NONVOLATILE MEMORY DEVICE AND SUB-BLOCK MANAGING METHOD THEREOF 审中-公开
    非易失性存储器件及其子块管理方法

    公开(公告)号：US20150149710A1

    公开(公告)日：2015-05-28

    申请号：US14610512

    申请日：2015-01-30

    申请人： EUN CHU OH ,  JUNJIN KONG

    发明人： EUN CHU OH ,  JUNJIN KONG

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0246 ,  G06F2212/7205 ,  G11C16/0483 ,  G11C16/14 ,  G11C16/16 ,  G11C16/3418 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

    摘要： A nonvolatile memory device includes a memory block, a row decoder, a voltage generator and control logic. The memory block includes memory cells stacked in a direction intersecting a substrate, the memory block being divided into sub-blocks configured to be erased independently. The row decoder is configured to select the memory block by a sub-block unit. The voltage generator is configured to generate an erase word line voltage to be provided to a first word line of a selected sub-block of the sub-blocks and a cut-off voltage, higher than the erase word line voltage, to be provided to a second word line of the selected sub-block during an erase operation. The control logic is configured to control the row decoder and the voltage generator to perform an erase operation on the selected sub-block.

    摘要翻译： 非易失性存储器件包括存储器块，行解码器，电压发生器和控制逻辑。 存储块包括在与衬底相交的方向上堆叠的存储单元，该存储块被分成被独立地擦除的子块。 行解码器被配置为通过子块单元选择存储块。 电压发生器被配置为产生要提供给子块的所选子块的第一字线的擦除字线电压和高于擦除字线电压的截止电压，以提供给 在擦除操作期间所选子块的第二字线。 控制逻辑被配置为控制行解码器和电压发生器对所选择的子块执行擦除操作。

    STORAGE DEVICE AND METHOD OF WRITING AND READING THE SAME
    7.
    发明申请
    STORAGE DEVICE AND METHOD OF WRITING AND READING THE SAME 有权
    存储装置及其写入和读取方法

    公开(公告)号：US20150006791A1

    公开(公告)日：2015-01-01

    申请号：US14297093

    申请日：2014-06-05

    申请人： Younggeon YOO ,  Junjin KONG ,  Hong Rak SON

    发明人： Younggeon YOO ,  Junjin KONG ,  Hong Rak SON

    IPC分类号： G06F12/02

    CPC分类号： G11C16/10 ,  G06F11/1072 ,  G11C11/5628 ,  G11C16/0483

    摘要： A write method of a storage device including at least one nonvolatile memory device and a memory controller controlling the nonvolatile memory device includes dividing write data into a plurality of page data groups, each page data group including multiple bits of data; encoding the divided page data groups using different binary codes, respectively; mapping the encoded page data groups; programming, in first memory cells connected to one word line, programming states to which binary values of each of the mapped encoded page data groups are mapped, such that, the plurality of page data groups correspond respectively to a plurality of read voltage levels, and for each of the plurality of page data groups, the page data group can be read by performing a single read operation on the first memory cells using the read voltage level corresponding to the page data group.

    摘要翻译： 一种存储装置的写入方法，包括至少一个非易失性存储器件和控制非易失性存储器件的存储器控​​制器，包括将写入数据划分成多个页数据组，每个页数据组包括多位数据; 分别使用不同的二进制码对分割页数据组进行编码; 映射编码页数据组; 在连接到一个字线的第一存储器单元中对编程状态进行编程，对每个映射编码页数据组的二进制值进行映射的编程状态，使得多个页数据组分别对应于多个读电压电平，以及 对于多个页面数据组中的每一个，可以通过使用与页面数据组对应的读取电压电平对第一存储器单元执行单个读取操作来读取页面数据组。

    NONVOLATILE MEMORY MODULES AND AUTHORIZATION SYSTEMS AND OPERATING METHODS THEREOF
    9.
    发明申请
    NONVOLATILE MEMORY MODULES AND AUTHORIZATION SYSTEMS AND OPERATING METHODS THEREOF 有权
    非易失性存储器模块和授权系统及其操作方法

    公开(公告)号：US20140157006A1

    公开(公告)日：2014-06-05

    申请号：US14091684

    申请日：2013-11-27

    申请人： Kwanghoon KIM ,  Seongsik HWANG ,  Junjin KONG ,  Dongsoo JUN

    发明人： Kwanghoon KIM ,  Seongsik HWANG ,  Junjin KONG ,  Dongsoo JUN

    IPC分类号： G06F12/14

    CPC分类号： G06F12/1433 ,  G06F21/64 ,  G06F2212/202

    摘要： Memory modules and authorization systems include a nonvolatile memory, an authentication engine configured to receive an initialization request from a user system, configured to generate a certification value based on device identifiers of devices includes in the user system in response to the initialization request and configured to control access to the nonvolatile memory based on the certification value, and a certification value storage configured to store the certification value.

    摘要翻译： 存储器模块和授权系统包括非易失性存储器，被配置为从用户系统接收初始化请求的认证引擎，被配置为基于设备的设备标识符生成认证值，所述设备标识符响应于初始化请求而包括在用户系统中并被配置为 基于所述认证值控制对所述非易失性存储器的访问，以及认证值存储器，被配置为存储所述认证值。

    MEMORY CONTROLLER CHANGING PARTIAL DATA IN MEMORY DEVICE AND METHOD FOR CHANGING PARTIAL DATA THEREOF
    10.
    发明申请
    MEMORY CONTROLLER CHANGING PARTIAL DATA IN MEMORY DEVICE AND METHOD FOR CHANGING PARTIAL DATA THEREOF 有权
    存储器控制器更改存储器件中的部分数据和更改其部分数据的方法

    公开(公告)号：US20140136920A1

    公开(公告)日：2014-05-15

    申请号：US14071771

    申请日：2013-11-05

    申请人： Kijun LEE ,  Junjin KONG ,  Hong Rak SON ,  Sejin LIM

    发明人： Kijun LEE ,  Junjin KONG ,  Hong Rak SON ,  Sejin LIM

    IPC分类号： G06F11/10

    CPC分类号： G06F11/1048 ,  G06F11/1076 ,  G06F11/1435 ,  G06F12/0804 ,  G06F12/0868 ,  H03M13/09 ,  H03M13/2942

    摘要： A partial data changing method of a memory controller includes receiving a request to change partial data from a host; detecting an error of old data, the old data being partial data read from a memory device using an error detection code; if the old data is not erroneous, calculating a data difference between new data provided from the host and the old data, and calculating a new parity using the data difference and an old parity read from the memory device; and storing the new data and the new parity at the memory device.

    摘要翻译： 存储器控制器的部分数据改变方法包括从主机接收改变部分数据的请求; 检测旧数据的错误，旧数据是使用错误检测码从存储装置读取的部分数据; 如果旧数据不是错误的，则计算从主机提供的新数据与旧数据之间的数据差异，并且使用从存储器件读取的数据差和旧奇偶校验来计算新奇偶校验; 以及将新数据和新奇偶校验存储在存储器件中。