公开(公告)号：US07504309B2

公开(公告)日：2009-03-17

申请号：US11548842

申请日：2006-10-12

Applicant: Thomas W. Dyer ,  Sunfei Fang ,  Jiang Yan ,  Jun Jung Kim ,  Yaocheng Liu ,  Huilong Zhu

Inventor： Thomas W. Dyer ,  Sunfei Fang ,  Jiang Yan ,  Jun Jung Kim ,  Yaocheng Liu ,  Huilong Zhu

IPC: H01L21/336

CPC classification number: H01L29/665 ,  H01L21/32 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6659

Abstract: A method forms a gate conductor over a substrate, and simultaneously forms spacers on sides of the gate conductor and a gate cap on the top of the gate conductor. Isolation regions are formed in the substrate and the method implants an impurity into exposed regions of the substrate not protected by the gate conductor and the spacers to form source and drain regions. The method deposits a mask over the gate conductor, the spacers, and the source and drain regions. The mask is recessed to a level below a top of the gate conductor but above the source and drain regions, such that the spacers are exposed and the source and drain regions are protected by the mask. With the mask in place, the method then safely removes the spacers and the gate cap, without damaging the source/drain regions or the isolation regions (which are protected by the mask). Next, the method removes the mask and then forms silicide regions on the gate conductor and the source and drain regions.

Abstract translation: 一种方法在衬底上形成栅极导体，同时在栅极导体的侧面和栅极导体的顶部上形成栅极盖。 在衬底中形成隔离区域，并且该方法将杂质注入未被栅极导体和间隔物保护的衬底的暴露区域中以形成源区和漏区。 该方法在栅极导体，间隔物以及源极和漏极区域上沉积掩模。 掩模凹陷到栅极导体的顶部下方但在源极和漏极区域之上的水平面，使得间隔物被暴露，并且源极和漏极区域被掩模保护。 在掩模就位的情况下，该方法然后安全地去除间隔物和栅极盖，而不损坏源极/漏极区域或隔离区域（被掩模保护）。 接下来，该方法移除掩模，然后在栅极导体和源极和漏极区域上形成硅化物区域。

公开(公告)号：US20080220584A1

公开(公告)日：2008-09-11

申请号：US11683590

申请日：2007-03-08

Applicant: Jun-jung Kim ,  Ja-hum Ku ,  Jae-eon Park ,  Sunfei Fang ,  Alois Gutmann ,  O-sung Kwon ,  Johnny Widodo ,  Dae-won Yang

Inventor： Jun-jung Kim ,  Ja-hum Ku ,  Jae-eon Park ,  Sunfei Fang ,  Alois Gutmann ,  O-sung Kwon ,  Johnny Widodo ,  Dae-won Yang

IPC: H01L29/82

CPC classification number: H01L21/0217 ,  C23C16/56 ,  H01L21/02211 ,  H01L21/02266 ,  H01L21/02274 ,  H01L21/31051 ,  H01L21/3185 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76837 ,  H01L21/823425

Abstract: Methods of forming integrated circuit devices include depositing an electrically insulating layer onto an integrated circuit substrate having integrated circuit structures thereon. This deposition step results in the formation of an electrically insulating layer having an undulating surface profile, which includes at least one peak and at least on valley adjacent to the at least one peak. A non-uniform thickening step is then performed. This non-uniform thickening step includes thickening a portion of the electrically insulating layer by redepositing portions of the electrically insulating layer from the least one peak to the at least one valley. This redeposition occurs using a sputter deposition technique that utilizes the electrically insulating layer as a sputter target.

Abstract translation: 形成集成电路器件的方法包括在其上具有集成电路结构的集成电路衬底上沉积电绝缘层。 该沉积步骤导致形成具有起伏表面轮廓的电绝缘层，该电绝缘层包括至少一个峰和至少与至少一个峰相邻的峰。 然后进行非均匀的增稠步骤。 这种不均匀的增厚步骤包括通过将电绝缘层的部分从至少一个峰重新沉积到至少一个谷部来增厚电绝缘层的一部分。 使用利用电绝缘层作为溅射靶的溅射沉积技术发生这种再沉积。

公开(公告)号：US20080173934A1

公开(公告)日：2008-07-24

申请号：US12048994

申请日：2008-03-14

Applicant: Jae Gon Lee ,  Jong Ho Yang ,  Victor Chan ,  Jun Jung Kim

Inventor： Jae Gon Lee ,  Jong Ho Yang ,  Victor Chan ,  Jun Jung Kim

IPC: H01L27/092

CPC classification number: H01L29/7833 ,  H01L21/823807 ,  H01L21/823864 ,  H01L27/0629 ,  H01L27/092 ,  H01L29/165 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66636 ,  H01L29/7843 ,  H01L29/7848

Abstract: An integrated circuit system that includes: providing a substrate including a first region with a first device and a second device and a second region with a resistance device; configuring the first device, the second device, and the resistance device to include a first spacer and a second spacer; forming a stress inducing layer over the first region and the second region; processing at least a portion of the stress inducing layer formed over the first region to alter the stress within the stress inducing layer; and forming a third spacer adjacent the second spacer of the first device and the second device from the stress inducing layer.

Abstract translation: 一种集成电路系统，包括：提供包括具有第一装置的第一区域的基板和具有电阻装置的第二区域; 配置第一装置，第二装置和电阻装置以包括第一间隔件和第二间隔件; 在所述第一区域和所述第二区域上形成应力诱导层; 处理形成在第一区域上的应力诱导层的至少一部分，以改变应力诱导层内的应力; 以及从所述应力诱导层形成邻近所述第一器件和所述第二器件的第二间隔物的第三间隔物。

公开(公告)号：US07297584B2

公开(公告)日：2007-11-20

申请号：US11246471

申请日：2005-10-07

Applicant: Jae-Eon Park ,  Ja-Hum Ku ,  Jun-Jung Kim ,  Dae-Kwon Kang ,  Young Way Teh

Inventor： Jae-Eon Park ,  Ja-Hum Ku ,  Jun-Jung Kim ,  Dae-Kwon Kang ,  Young Way Teh

IPC: H01L21/8234 ,  H01L21/8238 ,  H01L21/336

CPC classification number: H01L21/823807 ,  H01L21/0217 ,  H01L21/02274 ,  H01L21/268 ,  H01L21/3185 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/823864 ,  H01L29/7843

Abstract: In a semiconductor device having a dual stress liner for improving electron mobility, the dual stress liner includes a first liner portion formed on a PMOSFET and a second liner portion formed on an NMOSFET. The first liner portion has a first compressive stress, and the second liner portion has a second compressive stress smaller than the first compressive stress. The dual stress liner may be formed by forming a stress liner on a semiconductor substrate on which the PMOSFET and the NMOSFET are formed and selectively exposing a portion of the stress liner on the NMOSFET.

Abstract translation: 在具有用于改善电子迁移率的双应力衬垫的半导体器件中，双应力衬垫包括形成在PMOSFET上的第一衬垫部分和形成在NMOSFET上的第二衬垫部分。 第一衬里部分具有第一压缩应力，并且第二衬套部分具有小于第一压缩应力的第二压缩应力。 双应力衬垫可以通过在其上形成PMOSFET和NMOSFET的半导体衬底上形成应力衬垫而形成，并且选择性地暴露在NMOSFET上的应力衬垫的一部分。

公开(公告)号：US08227308B2

公开(公告)日：2012-07-24

申请号：US12647806

申请日：2009-12-28

Applicant: Ha-Jin Lim ,  Dong-Suk Shin ,  Pan-Kwi Park ,  Jun-Jung Kim ,  Tae-Gyun Kim

Inventor： Ha-Jin Lim ,  Dong-Suk Shin ,  Pan-Kwi Park ,  Jun-Jung Kim ,  Tae-Gyun Kim

IPC: H01L21/8238

CPC classification number: H01L21/28518 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7843

Abstract: A method of fabricating a semiconductor integrated circuit (IC) device can include forming a first silicide layer on at least a portion of a transistor on a substrate, forming nitrogen in the first silicide layer to form a second silicide layer, forming a first stress layer having a tensile stress on the substrate having the transistor formed thereon, and irradiating the first stress layer with ultraviolet (UV) light to form a second stress layer having greater tensile stress than the first stress layer.

Abstract translation: 制造半导体集成电路（IC）器件的方法可以包括在衬底上的晶体管的至少一部分上形成第一硅化物层，在第一硅化物层中形成氮以形成第二硅化物层，形成第一应力层 在其上形成有晶体管的衬底上具有拉伸应力，并且用紫外线（UV）光照射第一应力层以形成具有比第一应力层更大的拉伸应力的第二应力层。

公开(公告)号：US07785950B2

公开(公告)日：2010-08-31

申请号：US11164114

申请日：2005-11-10

Applicant: Sunfei Fang ,  Jun Jung Kim ,  Zhijiong Luo ,  Hung Y. Ng ,  Nivo Rovedo ,  Young Way Teh

Inventor： Sunfei Fang ,  Jun Jung Kim ,  Zhijiong Luo ,  Hung Y. Ng ,  Nivo Rovedo ,  Young Way Teh

IPC: H01L21/8238 ,  H01L21/469

CPC classification number: H01L21/823864 ,  H01L21/823807

Abstract: A method for providing a dual stress memory technique in a semiconductor device including an nFET and a PFET and a related structure are disclosed. One embodiment of the method includes forming a tensile stress layer over the nFET and a compressive stress layer over the pFET, annealing to memorize stress in the semiconductor device and removing the stress layers. The compressive stress layer may include a high stress silicon nitride deposited using a high density plasma (HDP) deposition method. The annealing step may include using a temperature of approximately 400-1200° C. The high stress compressive silicon nitride and/or the anneal temperatures ensure that the compressive stress memorization is retained in the pFET.

Abstract translation: 公开了一种在包括nFET和PFET以及相关结构的半导体器件中提供双重应力记忆技术的方法。 该方法的一个实施例包括在nFET上形成拉伸应力层，并在pFET上形成压应力层，退火以在半导体器件中记忆应力并去除应力层。 压应力层可以包括使用高密度等离子体（HDP）沉积方法沉积的高应力氮化硅。 退火步骤可以包括使用约400-1200℃的温度。高应力压缩氮化硅和/或退火温度确保压应力记忆保留在pFET中。

公开(公告)号：US07585773B2

公开(公告)日：2009-09-08

申请号：US11556591

申请日：2006-11-03

Applicant: Sunfei Fang ,  Jun Jung Kim ,  Thomas Dyer

Inventor： Sunfei Fang ,  Jun Jung Kim ,  Thomas Dyer

IPC: H01L29/72

CPC classification number: H01L21/823807 ,  H01L29/7843

Abstract: A semiconductor device is provided wherein at least one offset spacer is reduced and a non-conformal stress liner is thereafter deposited. By depositing the non-conformal stress liner in accordance with the present invention in close stress proximity to the FET, the carrier mobility and the performance of said device is significantly enhanced. The present invention is her directed to a method of fabricating said semiconductor device.

Abstract translation: 提供半导体器件，其中至少一个偏移间隔物被还原，然后沉积非共形应力衬垫。 通过在紧邻FET附近的紧压下沉积根据本发明的非共形应力衬垫，显着提高了所述器件的载流子迁移率和性能。 本发明是针对制造所述半导体器件的方法。

公开(公告)号：US20090098706A1

公开(公告)日：2009-04-16

申请号：US11871602

申请日：2007-10-12

Applicant: Jun-jung Kim ,  Joo-chan Kim ,  Jae-eon Park ,  Richard Anthony Conti ,  Zhao Lun ,  Johnny Widodo ,  William C. Wille ,  Biao Zuo

Inventor： Jun-jung Kim ,  Joo-chan Kim ,  Jae-eon Park ,  Richard Anthony Conti ,  Zhao Lun ,  Johnny Widodo ,  William C. Wille ,  Biao Zuo

IPC: H01L21/762

CPC classification number: H01L21/3105 ,  H01L21/76229 ,  H01L21/76232

Abstract: Methods of forming integrated circuit devices include forming a trench in a surface of semiconductor substrate and filling the trench with an electrically insulating region having a seam therein. The trench may be filled by depositing a sufficiently thick electrically insulating layer on sidewalls and a bottom of the trench. Curing ions are then implanted into the electrically insulating region at a sufficient energy and dose to reduce a degree of atomic order therein. The curing ions may be ones selected from a group consisting of nitrogen (N), phosphorus (P), boron (B), arsenic (As), carbon (C), argon (Ar), germanium (Ge), helium (He), neon (Ne) and xenon (Xe). These curing ions may be implanted at an energy of at least about 80 KeV and a dose of at least about 5×1014 ions/cm2. The electrically insulating region is then annealed at a sufficient temperature and for a sufficient duration to increase a degree of atomic order within the electrically insulating region.

Abstract translation: 形成集成电路器件的方法包括在半导体衬底的表面中形成沟槽，并用其中具有接缝的电绝缘区填充沟槽。 可以通过在沟槽的侧壁和底部上沉积足够厚的电绝缘层来填充沟槽。 然后将固化离子以足够的能量和剂量注入电绝缘区域以减少其中原子序列的程度。 固化离子可以是选自氮（N），磷（P），硼（B），砷（As），碳（C），氩（Ar），锗（Ge），氦 ），氖（Ne）和氙（Xe）。 这些固化离子可以以至少约80KeV的能量和至少约5×1014个离子/ cm 2的剂量注入。 然后将电绝缘区域在足够的温度下退火并持续足够的时间以增加电绝缘区域内的原子级数。

公开(公告)号：US20080142897A1

公开(公告)日：2008-06-19

申请号：US11613149

申请日：2006-12-19

Applicant: Young Way Teh ,  Xiangdong Chen ,  Jamin F. Fen ,  Jun Jung Kim ,  Daewon Yang ,  Roman Knoefler ,  Michael P. Belyansky

Inventor： Young Way Teh ,  Xiangdong Chen ,  Jamin F. Fen ,  Jun Jung Kim ,  Daewon Yang ,  Roman Knoefler ,  Michael P. Belyansky

IPC: H01L27/092

CPC classification number: H01L21/823807 ,  H01L29/7843

Abstract: An integrated circuit system is provided including forming a circuit element on a wafer, forming a stress formation layer having a non-uniform profile over the wafer, and forming an interlayer dielectric over the stress formation layer and the wafer.

Abstract translation: 提供了一种集成电路系统，包括在晶片上形成电路元件，在晶片上形成具有不均匀轮廓的应力形成层，并在应力形成层和晶片上形成层间电介质。

公开(公告)号：US20080122003A1

公开(公告)日：2008-05-29

申请号：US11556591

申请日：2006-11-03

Applicant: Sunfei Fang ,  Jun Jung Kim ,  Thomas Dyer

Inventor： Sunfei Fang ,  Jun Jung Kim ,  Thomas Dyer

IPC: H01L27/092 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L21/823807 ,  H01L29/7843

Abstract: A semiconductor device is provided wherein at least one offset spacer is reduced and a non-conformal stress liner is thereafter deposited. By depositing the non-conformal stress liner in accordance with the present invention in close stress proximity to the FET, the carrier mobility and the performance of said device is significantly enhanced. The present invention is her directed to a method of fabricating said semiconductor device.

Abstract translation: 提供半导体器件，其中至少一个偏移间隔物被还原，然后沉积非共形应力衬垫。 通过在紧邻FET附近的紧压下沉积根据本发明的非共形应力衬垫，显着提高了所述器件的载流子迁移率和性能。 本发明是针对制造所述半导体器件的方法。