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    Method For Forming Magnetic Tunnel Junction Structure And Method For Forming Magnetic Random Access Memory Using The Same
    2.
    发明申请
    Method For Forming Magnetic Tunnel Junction Structure And Method For Forming Magnetic Random Access Memory Using The Same 有权
    用于形成磁隧道结结构的方法和用于形成磁性随机存取存储器的方法

    公开(公告)号：US20120135543A1

    公开(公告)日：2012-05-31

    申请号：US13286630

    申请日：2011-11-01

    申请人： Hee-Ju SHIN ,  Jun-Ho JEONG ,  Jang-Eun LEE ,  Se-Chung OH

    发明人： Hee-Ju SHIN ,  Jun-Ho JEONG ,  Jang-Eun LEE ,  Se-Chung OH

    IPC分类号： H01L43/12

    CPC分类号： H01L43/12 ,  G11C11/161 ,  H01L27/228

    摘要： A method of fabricating a magnetic tunnel junction structure includes forming a magnetic tunnel junction layer on a substrate. A mask pattern is formed on a region of the second magnetic layer. A magnetic tunnel junction layer pattern and a sidewall dielectric layer pattern on at least one sidewall of the magnetic tunnel junction layer pattern are formed by performing at least one etch process and at least one oxidation process multiple times. The at least one etch process may include a first etch process to etch a portion of the magnetic tunnel junction layer using an inert gas and the mask pattern to form a first etch product. The at least one oxidation process may include a first oxidation process to oxidize the first etch product attached on an etched side of the magnetic tunnel junction layer.

    摘要翻译： 制造磁性隧道结结构的方法包括在衬底上形成磁性隧道结层。 在第二磁性层的区域上形成掩模图案。 通过多次执行至少一个蚀刻工艺和至少一个氧化工艺来形成在磁性隧道结层图案的至少一个侧壁上的磁性隧道结层图案和侧壁电介质层图案。 所述至少一个蚀刻工艺可以包括使用惰性气体蚀刻磁性隧道结层的一部分并且掩模图案以形成第一蚀刻产物的第一蚀刻工艺。 所述至少一个氧化工艺可以包括第一氧化工艺以氧化附着在磁性隧道结层的蚀刻侧上的第一蚀刻产物。

    Methods of forming resistive memory devices
    4.
    发明授权
    Methods of forming resistive memory devices 有权
    形成电阻式存储器件的方法

    公开(公告)号：US08058097B2

    公开(公告)日：2011-11-15

    申请号：US12784230

    申请日：2010-05-20

    申请人： Jang-Eun Lee ,  Dae-Kyom Kim ,  Jun-Ho Jeong ,  Se-Chung Oh ,  Kyung-Tae Nam ,  Hyun-Jun Sim

    发明人： Jang-Eun Lee ,  Dae-Kyom Kim ,  Jun-Ho Jeong ,  Se-Chung Oh ,  Kyung-Tae Nam ,  Hyun-Jun Sim

    IPC分类号： H01L21/36

    CPC分类号： H01L45/04 ,  H01L27/2418 ,  H01L45/1233 ,  H01L45/1253 ,  H01L45/146 ,  H01L45/1633

    摘要： Methods of forming a resistive memory device include forming an insulation layer on a semiconductor substrate including a conductive pattern, forming a contact hole in the insulation layer to expose the conductive pattern, forming a lower electrode in the contact hole, forming a variable resistive oxide layer in the contact hole on the lower electrode, forming a middle electrode in the contact hole on the variable resistive oxide layer, forming a buffer oxide layer on the middle electrode and the insulation layer, and forming an upper electrode on the buffer oxide layer. Related resistive memory devices are also disclosed.

    摘要翻译： 形成电阻性存储器件的方法包括在包括导电图案的半导体衬底上形成绝缘层，在绝缘层中形成接触孔以露出导电图案，在接触孔中形成下电极，形成可变电阻氧化物层 在下电极的接触孔中，在可变电阻氧化物层的接触孔中形成中间电极，在中间电极和绝缘层上形成缓冲氧化物层，在缓冲氧化物层上形成上电极。 还公开了相关的电阻式存储器件。

    UV nanoimprint lithography process and apparatus
    5.
    发明授权
    UV nanoimprint lithography process and apparatus 有权
    UV纳米压印光刻工艺和装置

    公开(公告)号：US08025830B2

    公开(公告)日：2011-09-27

    申请号：US12626788

    申请日：2009-11-27

    申请人： Jun-Ho Jeong ,  HyonKee Sohn ,  Young-Suk Sim ,  Young-Jae Shin ,  Eung-Sug Lee ,  Kyung-Hyun Whang

    发明人： Jun-Ho Jeong ,  HyonKee Sohn ,  Young-Suk Sim ,  Young-Jae Shin ,  Eung-Sug Lee ,  Kyung-Hyun Whang

    IPC分类号： B29C59/00

    CPC分类号： G03F7/0002 ,  B29C35/0888 ,  B29C59/022 ,  B29C2035/0827 ,  B29C2059/023 ,  B82Y10/00 ,  B82Y30/00 ,  B82Y40/00 ,  Y10S977/887

    摘要： A UV nanoimprint lithography process and its apparatus that are able to repeatedly fabricates nanostructures on a substrate (wafer, UV-transparent plate) by using a stamp that is as large as or smaller than the substrate in size are provided. The apparatus includes a substrate chuck for mounting the substrate; a stamp made of UV-transparent materials and having more than two element stamps, wherein nanostructures are formed on the surface of each element stamp; a stamp chuck for mounting the stamp; a UV lamp unit for providing UV light to cure resist applied between the element stamps and the substrate; a moving unit for moving the substrate chuck or the stamp chuck to press the resist with the element stamps and substrate; and a pressure supply unit for applying pressurized gas to some selected regions of the substrate to help complete some incompletely filled element stamps.

    摘要翻译： 提供了能够通过使用尺寸大于或小于基板的印模来重复地在基板（晶片，UV透明板）上制造纳米结构的UV纳米压印光刻工艺及其装置。 该装置包括用于安装基板的基板卡盘; 由UV透明材料制成并具有多于两个元件印章的印章，其中纳米结构形成在每个元件印模的表面上; 用于安装印章的邮票卡盘; UV灯单元，用于提供UV光以固化施加在元件印记和基板之间的抗蚀剂; 移动单元，用于移动基板卡盘或印模卡盘以用元件印刷和基板按压抗蚀剂; 以及用于将加压气体施加到所述基板的某些选定区域以帮助完成一些未完全填充的元件印章的压力供应单元。

    Stamp for micro/nano imprint lithography using diamond-like carbon and method of fabricating the same
    6.
    发明授权
    Stamp for micro/nano imprint lithography using diamond-like carbon and method of fabricating the same 有权
    用于使用类金刚石碳的微/纳刻蚀平版印刷及其制造方法

    公开(公告)号：US07914693B2

    公开(公告)日：2011-03-29

    申请号：US11582461

    申请日：2006-10-18

    申请人： Jun-Ho Jeong ,  Young-Suk Sim ,  Ki-Don Kim ,  Dae-Geun Choi ,  Eung-Sug Lee

    发明人： Jun-Ho Jeong ,  Young-Suk Sim ,  Ki-Don Kim ,  Dae-Geun Choi ,  Eung-Sug Lee

    IPC分类号： B44C1/22

    CPC分类号： G03F7/0002 ,  B82Y10/00 ,  B82Y40/00

    摘要： The present invention relates to a micro/nano imprint lithography technique and in particular, to a stamp that is used in an UV-micro/nano imprint lithography process or thermal micro/nano imprint lithography process and a method for fabricating the stamp.The method for fabricating a stamp for micro/nano imprint lithography of the present invention includes i) depositing a thin film of diamond-like carbon on a substrate, ii) applying resist on the diamond-like carbon thin film, iii) patterning the resist, iv) etching the diamond-like carbon thin film by using the resist as a protective layer, and v) removing the resist.

    摘要翻译： 微型/纳米压印光刻技术本发明涉及一种微/纳米压印光刻技术，尤其涉及一种用于UV-微/纳刻印版光刻工艺或热微/纳印版光刻工艺的印模，以及一种用于制造印模的方法。 制造本发明的微/纳刻印光刻用印模的方法包括：i）在基板上沉积类金刚石碳薄膜，ii）在金刚石状碳薄膜上涂布抗蚀剂，iii）使抗蚀剂图案化 ，iv）通过使用抗蚀剂作为保护层来蚀刻类金刚石碳薄膜，以及v）除去抗蚀剂。

    RESISTIVE MEMORY DEVICES INCLUDING SELECTED REFERENCE MEMORY CELLS
    10.
    发明申请
    RESISTIVE MEMORY DEVICES INCLUDING SELECTED REFERENCE MEMORY CELLS 失效
    包括选择的参考存储器单元的电阻存储器件

    公开(公告)号：US20090067216A1

    公开(公告)日：2009-03-12

    申请号：US12265941

    申请日：2008-11-06

    申请人： Hyun-Jo Kim ,  Kyung-Tae Nam ,  In-Gyu Baek ,  Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Ho Jeong

    发明人： Hyun-Jo Kim ,  Kyung-Tae Nam ,  In-Gyu Baek ,  Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Ho Jeong

    IPC分类号： G11C11/00 ,  G11C11/02 ,  G11C7/00

    CPC分类号： G11C11/1675 ,  G11C11/1673

    摘要： A magnetic memory cell array device can include a first current source line extending between pluralities of first and second memory cells configured for respective simultaneous programming and configured to conduct adequate programming current for writing one of the pluralities of first and second memory cells, a first current source transistor coupled to the first current source line and to a word line, a programming conductor coupled to the first current source transistor and extending across bit lines coupled to the one of the pluralities of first and second memory cells, configured to conduct the programming current across the bit lines, a second current source transistor coupled to the programming conductor and configured to switch the programming current from the programming conductor to a second current source transistor output, a second current source line extending adjacent the one of the pluralities of first and second memory cells opposite the first current source line, a first bias circuit configured to apply a first bias voltage to the first or second memory cells selected for accessed during a read operation, and a second bias circuit configured to apply a second bias voltage to the first or second memory cells unselected for access during the read operation.

    摘要翻译： 磁存储单元阵列器件可以包括在多个第一和第二存储器单元之间延伸的第一电流源线，该第一和第二存储器单元被配置用于相应的同时编程，并且被配置为进行用于写入多个第一和第二存储器单元之一的足够的编程电流，第一电流 源极晶体管，耦合到第一电流源线和字线，编程导体，其耦合到第一电流源晶体管并且延伸跨越耦合到多个第一和第二存储器单元中的一个的位线，被配置为导通编程电流 耦合到编程导体并被配置为将编程电流从编程导体切换到第二电流源晶体管输出的第二电流源晶体管，与多个第一和第二晶体管中的一个相邻延伸的第二电流源极线 与第一电流源线相对的存储单元，af 第一偏置电路，被配置为将第一偏置电压施加到在读取操作期间被选择访问的第一或第二存储器单元;以及第二偏置电路，被配置为将第二偏置电压施加到未被选择以在读取期间访问的第一或第二存储器单元 操作。