公开(公告)号：US5851890A

公开(公告)日：1998-12-22

申请号：US919394

申请日：1997-08-28

申请人： Jiunn-Yann Tsai ,  John Haywood ,  Ming Yi Lee

发明人： Jiunn-Yann Tsai ,  John Haywood ,  Ming Yi Lee

IPC分类号： H01L21/28 ,  H01L21/285 ,  H01L21/336 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L21/335

CPC分类号： H01L29/6659 ,  H01L21/28518 ,  H01L29/665 ,  H01L29/6656

摘要： A process for forming improved metal silicide contacts over the gate electrode and source/drain regions of MOS devices of an integrated circuit structure formed in a silicon substrate is described. The metal silicide contacts are formed by first forming a silicon oxide layer over exposed portions of the silicon substrate and over exposed surfaces of previously formed polysilicon gate electrodes. Silicon nitride sidewall spacers are then formed over the oxide on the sidewalls of the gate electrode by depositing a silicon nitride layer over the entire structure and then anisotropically etching the silicon nitride layer. Source/drain regions are then formed in the silicon substrate adjacent the nitride spacers and the structure is then contacted with an oxide etch to remove oxide from the upper surface of the gate electrode and the substrate surface over the source/drain regions. During the oxide etch step, notches, each having an aspect ratio of 1 or less, are formed in the exposed edges of the oxide respectively between the silicon nitride spacers and either the substrate or the gate electrode. A metal layer capable of reacting with the exposed silicon to form metal silicide contacts is then blanket deposited over the structure and into the notches. After reacting the metal with silicon surfaces with which it is in contact to form metal silicide, the unreacted metal is removed, leaving a metal silicide gate contact on the upper surface of the polysilicon gate electrode, as well as those upper portions of the sidewall of the gate electrode exposed by forming the notch in the oxide layer on the sidewall of the electrode. Metal silicide source/drain contacts of enlarged area are also formed over the exposed silicon surfaces of the source/drain regions and those portions of the silicon substrate beneath the nitride spacers exposed by the notches formed in the oxide beneath the nitride spacers.

公开(公告)号：US6147409A

公开(公告)日：2000-11-14

申请号：US98019

申请日：1998-06-15

申请人： Shouli Steve Hsia ,  Fred Chen ,  Jiunn-Yann Tsai

发明人： Shouli Steve Hsia ,  Fred Chen ,  Jiunn-Yann Tsai

IPC分类号： H01L21/768 ,  H01L23/532 ,  H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76844 ,  H01L21/76805 ,  H01L21/76838 ,  H01L23/53223 ,  H01L2924/0002

摘要： A composite metal line structure for an integrated circuit structure on a semiconductor substrate is disclosed which comprises: a low resistance metal core layer; a first thin protective layer of electrically conductive material on the upper surface of the metal core layer capable of protecting the metal core layer from reaction with tungsten; a layer of tungsten formed over the first protective layer to function as an etch stop layer for vias subsequently formed in an overlying dielectric layer; and a second thin protective layer of electrically conductive material over the tungsten layer and capable of functioning as an antireflective coating (ARC). When a dielectric layer is formed over the composite metal line structure, tungsten-filled vias can be formed in the dielectric layer which will extend down through the second thin protective layer to provide direct electrical contact between the tungsten-filled via and the tungsten layer of the composite metal line structure, thereby providing a low resistance contact between the tungsten-filled via and the composite metal line structure.

摘要翻译： 公开了一种用于半导体衬底上的集成电路结构的复合金属线结构，其包括：低电阻金属芯层; 金属芯层的上表面上的第一薄导电材料保护层，其能够保护金属芯层免受钨的反应; 形成在第一保护层上的钨层，用作随后在上覆介电层中形成的通孔的蚀刻停止层; 以及在钨层上方的能够用作抗反射涂层（ARC）的导电材料的第二薄保护层。 当在复合金属线结构上形成电介质层时，可以在电介质层中形成钨填充的通孔，该介电层将向下延伸穿过第二薄保护层，以在填充钨的通孔和钨层之间提供直接的电接触 复合金属线结构，从而在填充钨的通孔和复合金属线结构之间提供低电阻接触。

公开(公告)号：US6037262A

公开(公告)日：2000-03-14

申请号：US98032

申请日：1998-06-15

申请人： Shouli Steve Hsia ,  Jiunn-Yann Tsai

发明人： Shouli Steve Hsia ,  Jiunn-Yann Tsai

IPC分类号： H01L21/768 ,  H01L23/522 ,  H01L21/311

CPC分类号： H01L21/76808 ,  H01L23/5226 ,  H01L2221/1031 ,  H01L2924/0002

摘要： A process is disclosed for forming vias and trenches in two separate dielectric layers, which may be separated by an etch stop, while avoiding the etch mask stress complicated resist masks, or high aspect ratio openings of the prior art. A first dielectric layer 10 is formed over an integrated circuit structure 2 on a semiconductor substrate, and a thin second dielectric layer 20 is formed over the first dielectric layer. A first resist mask, is formed over the second dielectric layer, and the first and second dielectric layers are etched through to form one or more vias 18, 28 extending through both the first and second dielectric layers. The first resist mask is then removed and a third dielectric layer 70, having different etch characteristics than the second dielectric layer, is deposited over the structure. This third dielectric layer, which may comprise the same material as the first dielectric layer, is applied to the structure as a low step coverage, nonconformal coating layer which preferably does not completely fill the one or more vias already formed in the first and second dielectric layers. A second resist mask is then applied over the third dielectric layer and the third dielectric layer is etched through to the underlying second dielectric layer to form the desired trench openings 78, with the second dielectric material acting as an etch stop, and also as an etch mask for removal of any of the third dielectric layer material which has deposited in the via(s) previously formed in the first and second dielectric layers.

摘要翻译： 公开了一种用于在两个单独的电介质层中形成通路和沟槽的工艺，其可通过蚀刻停止层分开，同时避免了现有技术的蚀刻掩模应力复杂的抗蚀剂掩模或高纵横比开口。 第一电介质层10形成在半导体衬底上的集成电路结构2上，并且在第一介电层上形成薄的第二电介质层20。 第一抗蚀剂掩模形成在第二介电层上，并且第一和第二介电层被蚀刻通过以形成延伸穿过第一和第二介电层的一个或多个通孔18,28。 然后去除第一抗蚀剂掩模，并且在结构上沉积具有不同于第二介电层的蚀刻特性的第三介电层70。 该第三电介质层可以包括与第一电介质层相同的材料作为低阶覆盖，非共形涂层，优选地不完全填充已经形成在第一和第二电介质中的一个或多个通孔 层。 然后将第二抗蚀剂掩模施加在第三介电层上，并且第三电介质层被蚀刻到下面的第二介电层上以形成所需的沟槽开口78，第二介电材料用作蚀刻停止层，并且还作为蚀刻 掩模，用于去除沉积在先前形成在第一和第二电介质层中的通孔中的任何第三电介质层材料。

公开(公告)号：US6034401A

公开(公告)日：2000-03-07

申请号：US20029

申请日：1998-02-06

申请人： Shouli Hsia ,  Jiunn-Yann Tsai

发明人： Shouli Hsia ,  Jiunn-Yann Tsai

IPC分类号： H01L21/768 ,  H01L21/8238 ,  H01L23/485 ,  H01L29/94 ,  H01L23/52 ,  H01L29/41

CPC分类号： H01L23/485 ,  H01L21/76895 ,  H01L21/823842 ,  H01L21/823871 ,  H01L2924/0002

摘要： Disclosed is a process of electrically coupling the gate electrodes of an N-type transistor and a P-type transistor without causing substantial cross diffusion of P-type dopants into the N-type gate electrode and N-type dopants into the P-type gate electrode. This is possible because some or all annealing and diffusion steps are performed while the N-type and P-type gate electrodes are physically isolated from one another. Also disclosed is a Silicide as Diffusion Source process in which dopant atoms implanted in silicide regions diffuses out of the silicide regions and into the substrate to form source and drain diffusions. During this diffusion step adjacent N-type and P-type gate electrodes remain unconnected to prevent cross diffusion. Then, these two electrodes are electrically connected by a local interconnect. The local interconnection is a conductive path formed at about the level of the polysilicon (i.e., below a first metallization layer and above a substrate) and between two adjacent gate electrodes. In one case it is a tungsten plug formed in the space between an N-type polysilicon gate and a P-type polysilicon gate. In another case, it is a titanium nitride layer connecting the N-type and P-type polysilicon gates.

公开(公告)号：US6020242A

公开(公告)日：2000-02-01

申请号：US926590

申请日：1997-09-04

申请人： Jiunn-Yann Tsai ,  Shiuh-Luen Wang ,  Wen-Chin Yeh

发明人： Jiunn-Yann Tsai ,  Shiuh-Luen Wang ,  Wen-Chin Yeh

IPC分类号： H01L21/8242 ,  H01L21/336

CPC分类号： H01L27/10888 ,  H01L27/10894

摘要： A metal silicide blocking process for preventing formation of metal silicide on a first device and allowing formation of metal silicide on elements of a second device of an integrated circuit substrate is described. The process includes forming a gate electrode above the integrated circuit substrate, forming a first dielectric layer over the gate electrode and the substrate surface, forming a second dielectric layer above the first dielectric layer, etching anisotropically the second dielectric layer to form a second spacer portion adjacent to the first dielectric layer; masking the substrate surface of the first device to protect the first dielectric layer above the first device from being removed such that the substrate surface at the second device where the metal silicide is to be formed is exposed, etching the first dielectric layer to form a first spacer portion disposed between the gate electrode of the second device and the second spacer portion, the first spacer portion extends underneath the second spacer portion such that the first spacer portion is disposed between the second spacer portion and a portion of the substrate disposed beneath the second spacer portion, exposing the substrate surface of the first device, depositing a metal layer on the substrate surface and fusing metal ions from the metal layer with silicon ions from a plurality of device elements from the portion of the substrate surface where the metal silicide is to be formed to form metal silicide contact areas above the plurality of device elements.

摘要翻译： 描述了用于防止在第一器件上形成金属硅化物并且允许在集成电路衬底的第二器件的元件上形成金属硅化物的金属硅化物封装工艺。 该方法包括在集成电路衬底上形成栅电极，在栅电极和衬底表面上形成第一电介质层，在第一电介质层上形成第二电介质层，各向异性蚀刻第二电介质层以形成第二间隔部分 邻近第一电介质层; 掩蔽第一器件的衬底表面以保护第一器件上方的第一电介质层被去除，使得将要形成金属硅化物的第二器件处的衬底表面暴露，蚀刻第一介电层以形成第一 间隔部分设置在第二装置的栅电极和第二间隔部分之间，第一间隔部分在第二间隔部分下方延伸，使得第一间隔部分设置在第二间隔部分和布置在第二间隔部分下方的基底部分之间 间隔部分，暴露第一器件的衬底表面，在衬底表面上沉积金属层，并将来自金属层的金属离子与来自多个器件元件的硅离子从金属硅化物的衬底表面的部分 形成为在多个器件元件上方形成金属硅化物接触区域。

公开(公告)号：US06495408B1

公开(公告)日：2002-12-17

申请号：US09477170

申请日：2000-01-04

申请人： Shouli Hsia ,  Jiunn-Yann Tsai

发明人： Shouli Hsia ,  Jiunn-Yann Tsai

IPC分类号： H01L218238

CPC分类号： H01L23/485 ,  H01L21/76895 ,  H01L21/823842 ,  H01L21/823871 ,  H01L2924/0002 ,  H01L2924/00

摘要： Disclosed is a process of electrically coupling the gate electrodes of an N-type transistor and a P-type transistor without causing substantial cross diffusion of P-type dopants into the N-type gate electrode and N-type dopants into the P-type gate electrode. This is possible because some or all annealing and diffusion steps are performed while the N-type and P-type gate electrodes are physically isolated from one another. Also disclosed is a Silicide as Diffusion Source process in which dopant atoms implanted in silicide regions diffuses out of the silicide regions and into the substrate to form source and drain diffusions. During this diffusion step adjacent N-type and P-type gate electrodes remain unconnected to prevent cross diffusion. Then, these two electrodes are electrically connected by a local interconnect. The local interconnection is a conductive path formed at about the level of the polysilicon (i.e., below a first metallization layer and above a substrate) and between two adjacent gate electrodes. In one case it is a tungsten plug formed in the space between an N-type polysilicon gate and a P-type polysilicon gate. In another case, it is a titanium nitride layer connecting the N-type and P-type polysilicon gates.

摘要翻译： 公开了一种将N型晶体管和P型晶体管的栅电极电耦合的过程，而不会引起P型掺杂剂对N型栅电极和N型掺杂剂到P型栅极的显着交叉扩散 电极。 这是可能的，因为在N型和P型栅电极彼此物理隔离的同时执行一些或所有退火和扩散步骤。 还公开了硅化物作为扩散源工艺，其中注入硅化物区域的掺杂剂原子从硅化物区域扩散到衬底中以形成源极和漏极扩散。 在该扩散步骤期间，相邻的N型和P型栅电极保持不连接以防止交叉扩散。 然后，这两个电极通过局部互连电连接。 局部互连是在多晶硅的水平面（即，在第一金属化层的下方，衬底之下）和两个相邻的栅电极之间形成的导电通路。 在一种情况下，它是形成在N型多晶硅栅极和P型多晶硅栅极之间的空间中的钨插塞。 在另一种情况下，它是连接N型和P型多晶硅栅极的氮化钛层。

公开(公告)号：US6010952A

公开(公告)日：2000-01-04

申请号：US787992

申请日：1997-01-23

申请人： Jiunn-Yann Tsai ,  Zhihai Wang ,  Wen-Chin Yeh

发明人： Jiunn-Yann Tsai ,  Zhihai Wang ,  Wen-Chin Yeh

IPC分类号： H01L21/265 ,  H01L21/28 ,  H01L21/285 ,  H01L21/3205 ,  H01L21/336 ,  H01L23/52 ,  H01L29/78 ,  H01L29/10

CPC分类号： H01L29/665 ,  H01L21/26586 ,  H01L21/28176 ,  H01L21/28518 ,  H01L29/66575

摘要： An improved process is provided for amorphizing portions of a silicon substrate and a polysilicon gate electrode surface to be converted to metal silicide by subsequent reaction of the amorphized silicon with a metal layer applied over the silicon substrate and polysilicon gate electrode after the amorphizing step. The improvement comprises implanting the exposed surface of the silicon substrate and the surface of the polysilicon gate electrode with a beam of amorphizing ions at an angle of at least 15.degree. to a line perpendicular to the plane of the surface of the silicon substrate to thereby inhibit channeling of the implanted ions through the gate electrode to the underlying gate oxide and channel of the MOS structure. The implant angle of the beam of amorphizing ions is preferably at least 30.degree., but should not exceed 60.degree., with respect to a line perpendicular to the plane of the surface of the silicon substrate.

摘要翻译： 提供了一种改进的方法，用于通过随后非晶化硅与在非晶化步骤之后施加在硅衬底和多晶硅栅电极上的金属层的反应而将硅衬底和多晶硅栅极电极表面的非晶化部分转化为金属硅化物。 该改进包括将硅衬底的暴露表面和多晶硅栅电极的表面以与硅衬底的表面平面垂直的线至少15°的角度将非晶化离子束注入，从而抑制 将植入的离子通过栅电极引导到MOS结构的底层栅极氧化物和沟道。 相对于垂直于硅衬底表面平面的线，非晶化离子束的植入角度优选为至少30°，但不应超过60°。

公开(公告)号：US5874342A

公开(公告)日：1999-02-23

申请号：US890222

申请日：1997-07-09

申请人： Jiunn-Yann Tsai ,  Zhihai Wang ,  Yen-Hui Joseph Ku

发明人： Jiunn-Yann Tsai ,  Zhihai Wang ,  Yen-Hui Joseph Ku

IPC分类号： H01L29/78 ,  H01L21/225 ,  H01L21/336

CPC分类号： H01L29/66575 ,  H01L21/2257 ,  H01L29/665

摘要： A process which is capable of forming shallow source/drain regions in a silicon substrate and a doped gate electrode by implantation of cobalt silicide contacts of uniform thickness previously formed on the substrate followed by diffusion of the dopant into the substrate to form the desired source/drain regions, and into the polysilicon gate electrode to provide the desired conductivity is described. The process comprises: first depositing a layer of cobalt over a polysilicon gate electrode and areas of a silicon substrate where source/drain regions will be formed; then forming at least one capping layer over the cobalt layer; then annealing the structure at a first temperature to form cobalt silicide; then removing the capping layer, as well as the unreacted cobalt and any cobalt reaction products other than cobalt silicide; then annealing the structure again at a higher temperature than the first anneal to form high temperature cobalt silicide; then implanting the cobalt silicide with one or more dopants suitable for forming source/drain regions in the silicon substrate and for increasing the conductivity of the polysilicon gate electrode; and then heating the structure sufficiently to cause the implanted dopant or dopants in the cobalt silicide to diffuse into the substrate to form the desired source/drain regions and into the polysilicon gate electrode to increase the conductivity thereof.

摘要翻译： 能够通过在衬底上注入预先形成均匀厚度的钴硅化物触点，然后将掺杂剂扩散到衬底中以形成所需的源极/漏极区域，从而在硅衬底和掺杂栅电极中形成浅源极/漏极区域的工艺， 漏极区域和多晶硅栅电极以提供期望的导电性。 该方法包括：首先在多晶硅栅极上沉积一层钴，并在其上形成源极/漏极区的硅衬底区域; 然后在所述钴层上形成至少一个覆盖层; 然后在第一温度下退火该结构以形成硅化钴; 然后除去覆盖层，以及未反应的钴和除了硅化钴之外的任何钴反应产物; 然后在比第一退火更高的温度下再次退火结构以形成高温钴硅酸盐; 然后用适合于在硅衬底中形成源/漏区的一种或多种掺杂剂注入硅化钴，并增加多晶硅栅电极的导电性; 然后充分加热该结构，使得硅化钴中的注入的掺杂剂或掺杂剂扩散到衬底中以形成所需的源极/漏极区并进入多晶硅栅电极以增加其导电性。

公开(公告)号：US5024954A

公开(公告)日：1991-06-18

申请号：US505406

申请日：1990-04-06

申请人： Mao-Chieh Chen ,  Bing-Yue Tsui ,  Jiunn-Yann Tsai

发明人： Mao-Chieh Chen ,  Bing-Yue Tsui ,  Jiunn-Yann Tsai

IPC分类号： H01L21/265 ,  H01L21/285

CPC分类号： H01L21/26513 ,  H01L21/28518 ,  H01L21/28537

摘要： A method of improving the high temperature stability of PtSi/Si structure is disclosed. A sufficient amount of fluorine-contained ion is implanted into the PtSi/Si structure or Pt/Si structure or Si substrate. The characteristics of the resulted PtSi/Si structure remain unchanged even after annealing at 800.degree. C. in contrast to the conventional PtSi/Si structure whose characteristics start to degrade at 700.degree. C. All devices contacted by PtSi, either ohmic or Schottky contact, are able to withstand an 800.degree. C. high temperature treatment without degradation.

摘要翻译： 公开了一种提高PtSi / Si结构的高温稳定性的方法。 向PtSi / Si结构或Pt / Si结构或Si衬底中注入足够量的含氟离子。 所得到的PtSi / Si结构的特性即使在800℃退火后也保持不变，与常规的PtSi / Si结构相比，其特性在700℃开始降解。所有与PtSi接触的器件，欧姆或肖特基接触， 能耐受800℃高温处理而不降解。