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    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES HAVING DIFFERENT THICKNESS SILICON-GERMANIUM LAYERS
    1.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT DEVICES HAVING DIFFERENT THICKNESS SILICON-GERMANIUM LAYERS 有权
    具有不同厚度硅 - 锗层的半导体集成电路器件

    公开(公告)号：US20120228720A1

    公开(公告)日：2012-09-13

    申请号：US13476121

    申请日：2012-05-21

    申请人： Myung-Sun Kim ,  Hwa-Sung Rhee ,  Ho Lee ,  Ji-Hye Yi

    发明人： Myung-Sun Kim ,  Hwa-Sung Rhee ,  Ho Lee ,  Ji-Hye Yi

    IPC分类号： H01L27/088

    CPC分类号： H01L29/7848 ,  H01L21/02532 ,  H01L21/0262 ,  H01L21/02636 ,  H01L29/165 ,  H01L29/66636 ,  H01L29/78

    摘要： Methods of fabricating semiconductor integrated circuit devices are provided. A substrate is provided with gate patterns formed on first and second regions. Spaces between gate patterns on the first region are narrower than spaces between gate patterns on the second region. Source/drain trenches are formed in the substrate on opposite sides of the gate patterns on the first and second regions. A first silicon-germanium (SiGe) epitaxial layer is formed that partially fills the source/drain trenches using a first silicon source gas. A second SiGe epitaxial layer is formed directly on the first SiGe epitaxial layer to further fill the source/drain trenches using a second silicon source gas that is different from the first silicon source gas.

    摘要翻译： 提供制造半导体集成电路器件的方法。 基板设置有形成在第一和第二区域上的栅极图案。 第一区域上的栅极图案之间的间隔比第二区域上的栅极图案之间的空间窄。 源极/漏极沟槽在第一和第二区域上的栅极图案的相对侧上的衬底中形成。 形成第一硅锗（SiGe）外延层，其使用第一硅源气体部分地填充源极/漏极沟槽。 直接在第一SiGe外延层上形成第二SiGe外延层，以使用不同于第一硅源气体的第二硅源气体来进一步填充源/漏沟槽。

    Phase changeable structure and method of forming the same
    3.
    发明授权
    Phase changeable structure and method of forming the same 有权
    相变结构及其形成方法

    公开(公告)号：US07569430B2

    公开(公告)日：2009-08-04

    申请号：US11674580

    申请日：2007-02-13

    申请人： Jun-Soo Bae ,  Hideki Horii ,  Ji-Hye Yi ,  Young-Soo Lim

    发明人： Jun-Soo Bae ,  Hideki Horii ,  Ji-Hye Yi ,  Young-Soo Lim

    IPC分类号： H01L21/82

    CPC分类号： H01L45/1675 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/144

    摘要： The present invention relates to a phase changeable structure having decreased amounts of defects and a method of forming the phase changeable structure. A stacked composite is first formed by (i) forming a phase changeable layer including a chalcogenide is formed on a lower electrode, (ii) forming an etch stop layer having a first etch rate with respect to a first etching material including chlorine on the phase changeable layer, and (iii) forming a conductive layer having a second etch rate with respect to the first etching material on the etch stop layer. The conductive layer of the stacked composite is then etched using the first etching material to form an upper electrode. The etch stop layer and the phase changeable layer are then etched using a second etching material that is substantially flee of chlorine to form an etch stop pattern and a phase changeable pattern, respectively.

    摘要翻译： 本发明涉及具有减少的缺陷量的相变结构和形成相变结构的方法。 首先通过（i）在下电极上形成包括硫族化物的相变层来形成堆叠复合体，（ii）形成相对于在相上包括氯的第一蚀刻材料具有第一蚀刻速率的蚀刻停止层 可变层，和（iii）形成相对于蚀刻停止层上的第一蚀刻材料具有第二蚀刻速率的导电层。 然后使用第一蚀刻材料蚀刻层叠复合体的导电层以形成上电极。 然后使用基本上不含氯的第二蚀刻材料来蚀刻蚀刻停止层和相变层，以分别形成蚀刻停止图案和相变图案。

    Method of Manufacturing a Semiconductor Device
    4.
    发明申请
    Method of Manufacturing a Semiconductor Device 有权
    制造半导体器件的方法

    公开(公告)号：US20090170254A1

    公开(公告)日：2009-07-02

    申请号：US12343134

    申请日：2008-12-23

    申请人： Hwa-Sung Rhee ,  Ho Lee ,  Myung-Sun Kim ,  Ji-Hye Yi

    发明人： Hwa-Sung Rhee ,  Ho Lee ,  Myung-Sun Kim ,  Ji-Hye Yi

    IPC分类号： H01L21/8238

    CPC分类号： H01L21/823807 ,  H01L21/26506 ,  H01L21/823814 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7848

    摘要： In a method of manufacturing a semiconductor device, a first gate electrode and a second gate electrode are formed in a first area and a second area of a substrate. Non-crystalline regions are formed in the first area of the substrate adjacent the first gate electrode. A layer having a first stress is formed on the substrate and the first and the second gate electrodes. A mask is formed on a first portion of the layer in the first area of the substrate to expose a second portion of the layer in the second area. The second portion is etched to form a sacrificial spacer on a sidewall of the second gate electrode. The second area of the substrate is partially etched using the mask, the second gate electrode and the sacrificial spacer, to form recesses in the second area of the substrate adjacent the second gate electrode. Patterns having a second stress are formed in the recesses.

    摘要翻译： 在制造半导体器件的方法中，第一栅电极和第二栅电极形成在衬底的第一区域和第二区域中。 在与第一栅电极相邻的衬底的第一区域中形成非结晶区域。 在基板和第一和第二栅电极上形成具有第一应力的层。 掩模在衬底的第一区域中的该层的第一部分上形成以暴露第二区域中该层的第二部分。 蚀刻第二部分以在第二栅电极的侧壁上形成牺牲间隔物。 使用掩模，第二栅电极和牺牲隔离物部分蚀刻衬底的第二区域，以在与第二栅电极相邻的衬底的第二区域中形成凹陷。 在凹部中形成具有第二应力的图案。

    PHASE-CHANGEABLE MEMORY DEVICES
    5.
    发明申请
    PHASE-CHANGEABLE MEMORY DEVICES 有权
    相变存储器件

    公开(公告)号：US20080258128A1

    公开(公告)日：2008-10-23

    申请号：US12147996

    申请日：2008-06-27

    申请人： Bong-Jin Kuh ,  Yong-Ho Ha ,  Ji-Hye Yi

    发明人： Bong-Jin Kuh ,  Yong-Ho Ha ,  Ji-Hye Yi

    IPC分类号： H01L47/00

    CPC分类号： G11C13/0004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1608 ,  Y10S438/90

    摘要： A phase-changeable memory device includes a substrate having a contact region on an upper surface thereof. An insulating interlayer on the substrate has an opening therein, and a lower electrode is formed in the opening. The lower electrode has a nitrided surface portion and is in electrical contact with the contact region of the substrate. A phase-changeable material layer pattern is on the lower electrode, and an upper electrode is on the phase-changeable material layer pattern. The insulating interlayer may have a nitrided surface portion and the phase-changeable material layer may be at least partially on the nitrided surface portion of the insulating interlayer. Methods of forming phase-changeable memory devices are also disclosed.

    摘要翻译： 相变型存储器件包括在其上表面具有接触区域的衬底。 衬底上的绝缘中间层具有开口，并且在开口中形成下电极。 下电极具有氮化表面部分并且与衬底的接触区域电接触。 相变材料层图案位于下电极上，上电极位于相变材料层图案上。 绝缘中间层可以具有氮化表面部分，并且相变材料层可以至少部分地在绝缘中间层的氮化表面部分上。 还公开了形成相变存储器件的方法。

    Phase-changeable memory devices and methods of forming the same
    6.
    发明授权
    Phase-changeable memory devices and methods of forming the same 有权
    相变存储器件及其形成方法

    公开(公告)号：US07394087B2

    公开(公告)日：2008-07-01

    申请号：US11205742

    申请日：2005-08-17

    申请人： Bong-Jin Kuh ,  Yong-Ho Ha ,  Ji-Hye Yi

    发明人： Bong-Jin Kuh ,  Yong-Ho Ha ,  Ji-Hye Yi

    IPC分类号： H01L29/02

    CPC分类号： G11C13/0004 ,  H01L27/2436 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/126 ,  H01L45/144 ,  H01L45/1608 ,  Y10S438/90

    摘要： A phase-changeable memory device includes a substrate having a contact region on an upper surface thereof. An insulating interlayer on the substrate has an opening therein, and a lower electrode is formed in the opening. The lower electrode has a nitrided surface portion and is in electrical contact with the contact region of the substrate. A phase-changeable material layer pattern is on the lower electrode, and an upper electrode is on the phase-changeable material layer pattern. The insulating interlayer may have a nitrided surface portion and the phase-changeable material layer may be at least partially on the nitrided surface portion of the insulating interlayer. Methods of forming phase-changeable memory devices are also disclosed.

    摘要翻译： 相变型存储器件包括在其上表面具有接触区域的衬底。 衬底上的绝缘中间层具有开口，并且在开口中形成下电极。 下电极具有氮化表面部分并且与衬底的接触区域电接触。 相变材料层图案位于下电极上，上电极位于相变材料层图案上。 绝缘中间层可以具有氮化表面部分，并且相变材料层可以至少部分地在绝缘中间层的氮化表面部分上。 还公开了形成相变存储器件的方法。