公开(公告)号：US20110044113A1

公开(公告)日：2011-02-24

申请号：US12828480

申请日：2010-07-01

申请人： In-Mo KIM ,  Jae Yong JEONG

发明人： In-Mo KIM ,  Jae Yong JEONG

IPC分类号： G11C16/04

CPC分类号： G11C11/5628 ,  G11C16/12 ,  G11C16/349

摘要： A nonvolatile memory device performs a program operation on selected memory cells by determining a level of a program voltage based on a degree of deterioration of the memory cells, and executing the program operation using the program voltage.

摘要翻译： 非易失性存储器件通过基于存储器单元的劣化程度确定编程电压的电平，并使用编程电压执行编程操作来对所选存储单元执行编程操作。

公开(公告)号：US07787305B2

公开(公告)日：2010-08-31

申请号：US12134648

申请日：2008-06-06

申请人： In-Mo Kim ,  Jae-Yong Jeong ,  Chi-Weon Yoon

发明人： In-Mo Kim ,  Jae-Yong Jeong ,  Chi-Weon Yoon

IPC分类号： G11C16/04

CPC分类号： G11C16/10

摘要： A flash memory device includes a flash memory cell array having flash memory cells arranged with word and bit lines, a word line driver circuit configured to drive the word lines at a selected step increment during a programming operation, a bulk-voltage supply circuit configured to supply a bulk voltage into a bulk of the flash memory cell array and a writing circuit configured to drive the bit lines selected by conditions during a programming operation. A control logic block is configured to control the writing circuit and the bulk-voltage supply circuit during the programming operation. The control logic block is configured to cause the writing circuit and/or the bulk-voltage supply circuit to change at least one of the conditions of the writing circuit and/or the bulk voltage responsive to the selected step increment.

摘要翻译： 一种闪速存储器件包括：闪存单元阵列，具有布置有字线和位线的闪速存储器单元;字线驱动器电路，被配置为在编程操作期间以选定的阶跃增量驱动所述字线，所述体电压电源电路被配置为 将大容量电压提供到闪存单元阵列的大部分中;以及写入电路，其被配置为驱动在编程操作期间由条件选择的位线。 控制逻辑块被配置为在编程操作期间控制写入电路和体电压电源电路。 控制逻辑块被配置为使得写入电路和/或体电压电源电路响应于所选择的步进增量来改变写入电路和/或体电压的条件中的至少一个。

公开(公告)号：US20150287437A1

公开(公告)日：2015-10-08

申请号：US14578632

申请日：2014-12-22

申请人： ANSOO PARK ,  IN-MO KIM ,  JUNG-SEOK HWANG

发明人： ANSOO PARK ,  IN-MO KIM ,  JUNG-SEOK HWANG

IPC分类号： G11C5/02 ,  G11C5/06

CPC分类号： G11C5/025 ,  G11C8/14 ,  G11C11/1657 ,  G11C11/2257 ,  G11C13/0028 ,  G11C16/08 ,  G11C2213/71 ,  H01L27/11582

摘要： A nonvolatile memory device includes a first memory block connected to first word lines, a second memory block arranged in a direction perpendicular to the first memory block and is connected to second word lines, first pass transistors for enabling the first word lines, and second pass transistors for enabling the second word lines. The first and second pass transistors are arranged in a horizontal direction with respect to the first and second memory blocks.

摘要翻译： 非易失性存储器件包括连接到第一字线的第一存储器块，沿垂直于第一存储器块的方向布置的第二存储器块，并且连接到第二字线，用于使第一字线实现的第一通过晶体管和第二通道 用于启用第二字线的晶体管。 第一和第二传输晶体管相对于第一和第二存储器块在水平方向上布置。

公开(公告)号：US08154920B2

公开(公告)日：2012-04-10

申请号：US12712769

申请日：2010-02-25

申请人： In-Mo Kim ,  Jae-Yong Jeong

发明人： In-Mo Kim ,  Jae-Yong Jeong

IPC分类号： G11C16/04

CPC分类号： G11C16/34 ,  G11C11/5642 ,  G11C16/32

摘要： A method of reading data in a non-volatile memory device based on the logic level of a selection bit of an address, determines an order of reading a first and second bits of data stored in one multi-level memory cell corresponding to the address based on the logic level of the selection bit, and senses and outputs the first and second bits of data according to the determined order of reading. The method of reading data in a non-volatile memory device and the method of inputting and outputting data in a non-volatile memory device may reduce the initial read time by selecting the order of reading the first and second bits of data stored in the multi-level memory cell and reading the data according the order based on the start address.

摘要翻译： 一种基于地址的选择位的逻辑电平读取非易失性存储器件中的数据的方法，确定读取与基于地址对应的一个多级存储器单元中存储的数据的第一和第二位的顺序 在选择位的逻辑电平上，根据确定的读数顺序来感测和输出数据的第一和第二位。 在非易失性存储器件中读取数据的方法以及在非易失性存储器件中输入和输出数据的方法可以通过选择读取多重存储器中存储的数据的第一和第二位的顺序来减少初始读取时间 级存储单元，并根据开始地址按顺序读取数据。

公开(公告)号：US09576612B2

公开(公告)日：2017-02-21

申请号：US14578632

申请日：2014-12-22

申请人： Ansoo Park ,  In-Mo Kim ,  Jung-Seok Hwang

发明人： Ansoo Park ,  In-Mo Kim ,  Jung-Seok Hwang

IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C8/14 ,  G11C13/00 ,  G11C16/08 ,  G11C11/16 ,  G11C11/22 ,  H01L27/115

CPC分类号： G11C5/025 ,  G11C8/14 ,  G11C11/1657 ,  G11C11/2257 ,  G11C13/0028 ,  G11C16/08 ,  G11C2213/71 ,  H01L27/11582

摘要： A nonvolatile memory device includes a first memory block connected to first word lines, a second memory block arranged in a direction perpendicular to the first memory block and is connected to second word lines, first pass transistors for enabling the first word lines, and second pass transistors for enabling the second word lines. The first and second pass transistors are arranged in a horizontal direction with respect to the first and second memory blocks.

摘要翻译： 非易失性存储器件包括连接到第一字线的第一存储器块，沿垂直于第一存储器块的方向布置的第二存储器块，并且连接到第二字线，用于使第一字线实现的第一通过晶体管和第二通道 用于启用第二字线的晶体管。 第一和第二传输晶体管相对于第一和第二存储器块在水平方向上布置。

公开(公告)号：US09570446B1

公开(公告)日：2017-02-14

申请号：US14974275

申请日：2015-12-18

申请人： Hyo Seok Woo ,  In Mo Kim ,  Bora Lee ,  Sun Young Kim ,  Hoo Sung Cho

发明人： Hyo Seok Woo ,  In Mo Kim ,  Bora Lee ,  Sun Young Kim ,  Hoo Sung Cho

IPC分类号： H01L23/48 ,  G01R31/28 ,  H01L23/485 ,  G01R1/067 ,  H01L27/105 ,  H01L23/00 ,  H01L23/522 ,  H01L21/66

CPC分类号： H01L22/32 ,  G01R1/067 ,  G01R31/28 ,  G11C5/025 ,  G11C29/1201 ,  G11C29/48 ,  G11C2029/5602 ,  H01L22/34 ,  H01L24/09 ,  H01L2224/08055 ,  H01L2224/09055

摘要： A semiconductor device includes a plurality of semiconductor devices, a plurality of metal lines electrically connected to at least one of the semiconductor devices, and a protective layer on the metal lines. The protective layer includes a plurality of open areas partially exposing the metal lines and which serves as pads. A first pad includes a first area that extends from at least one of the metal lines and at least one second area around and separated from the first area.

摘要翻译： 半导体器件包括多个半导体器件，电连接到至少一个半导体器件的多个金属线以及金属线上的保护层。 保护层包括部分地露出金属线并用作垫的多个开放区域。 第一垫包括从金属线中的至少一个延伸的第一区域和围绕第一区域分离的至少一个第二区域。

公开(公告)号：US20090003075A1

公开(公告)日：2009-01-01

申请号：US12134648

申请日：2008-06-06

申请人： In-Mo Kim ,  Jae-Yong Jeong ,  Chi-Weon Yoon

发明人： In-Mo Kim ,  Jae-Yong Jeong ,  Chi-Weon Yoon

IPC分类号： G11C16/06

CPC分类号： G11C16/10

摘要： A flash memory device includes a flash memory cell array having flash memory cells arranged with word and bit lines, a word line driver circuit configured to drive the word lines at a selected step increment during a programming operation, a bulk-voltage supply circuit configured to supply a bulk voltage into a bulk of the flash memory cell array and a writing circuit configured to drive the bit lines selected by conditions during a programming operation. A control logic block is configured to control the writing circuit and the bulk-voltage supply circuit during the programming operation. The control logic block is configured to cause the writing circuit and/or the bulk-voltage supply circuit to change at least one of the conditions of the writing circuit and/or the bulk voltage responsive to the selected step increment.

摘要翻译： 一种闪速存储器件包括：闪存单元阵列，具有布置有字线和位线的闪速存储器单元;字线驱动器电路，被配置为在编程操作期间以选定的阶跃增量驱动所述字线，所述体电压电源电路被配置为 将大容量电压提供到闪存单元阵列的大部分中;以及写入电路，其被配置为驱动在编程操作期间由条件选择的位线。 控制逻辑块被配置为在编程操作期间控制写入电路和体电压电源电路。 控制逻辑块被配置为使得写入电路和/或体电压电源电路响应于所选择的步进增量来改变写入电路和/或体电压的条件中的至少一个。

公开(公告)号：US20100226172A1

公开(公告)日：2010-09-09

申请号：US12712769

申请日：2010-02-25

申请人： In-Mo Kim ,  Jae-Yong Jeong

发明人： In-Mo Kim ,  Jae-Yong Jeong

IPC分类号： G11C16/04

CPC分类号： G11C16/34 ,  G11C11/5642 ,  G11C16/32

摘要： A method of reading data in a non-volatile memory device based on the logic level of a selection bit of an address, determines an order of reading a first and second bits of data stored in one multi-level memory cell corresponding to the address based on the logic level of the selection bit, and senses and outputs the first and second bits of data according to the determined order of reading. The method of reading data in a non-volatile memory device and the method of inputting and outputting data in a non-volatile memory device may reduce the initial read time by selecting the order of reading the first and second bits of data stored in the multi-level memory cell and reading the data according the order based on the start address.

摘要翻译： 一种基于地址的选择位的逻辑电平读取非易失性存储器件中的数据的方法，确定读取与基于地址对应的一个多级存储器单元中存储的数据的第一和第二位的顺序 在选择位的逻辑电平上，根据确定的读数顺序来感测和输出数据的第一和第二位。 在非易失性存储器件中读取数据的方法以及在非易失性存储器件中输入和输出数据的方法可以通过选择读取多重存储器中存储的数据的第一和第二位的顺序来减少初始读取时间 级存储单元，并根据开始地址按顺序读取数据。