公开(公告)号：US20160013158A1

公开(公告)日：2016-01-14

申请号：US14718313

申请日：2015-05-21

申请人： Hyo-Soon KANG ,  SunWon KANG

发明人： Hyo-Soon KANG ,  SunWon KANG

IPC分类号： H01L25/065 ,  H01L23/498 ,  H01L23/31

CPC分类号： H01L25/0657 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/5386 ,  H01L24/06 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/105 ,  H01L2224/04042 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06558 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/15159 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package is provided. The semiconductor package includes a package substrate, a semiconductor chip, bonding wires, and a molding film. The package substrate includes a first surface having a recessed portion, a second surface opposed to the first surface, an opening extending from the recessed portion of the first surface to the second surface, and bonding pads provided on the first surface. The semiconductor chip is disposed on the second surface of the package substrate to cover the opening, and includes center pads exposed through the opening. Bonding wires electrically connect the center pads and the bonding pads through the opening. The molding film covers the bonding pads, the center pads, and the bonding wires. A depth of the recessed portion is greater than a distance between the recessed portion of the first surface and a lowermost surface of the molding film.

摘要翻译： 提供半导体封装。 半导体封装包括封装基板，半导体芯片，接合线和成型膜。 封装衬底包括具有凹部的第一表面，与第一表面相对的第二表面，从第一表面的凹部延伸到第二表面的开口以及设置在第一表面上的接合焊盘。 半导体芯片设置在封装基板的第二表面上以覆盖开口，并且包括通过开口暴露的中心焊盘。 接合线通过开口电连接中心焊盘和焊盘。 成型膜覆盖接合焊盘，中心焊盘和接合线。 凹部的深度大于第一表面的凹部与成型膜的最下表面之间的距离。

公开(公告)号：US09105503B2

公开(公告)日：2015-08-11

申请号：US14047120

申请日：2013-10-07

申请人： Yonghoon Kim ,  Hyo-Soon Kang ,  Inho Choi

发明人： Yonghoon Kim ,  Hyo-Soon Kang ,  Inho Choi

IPC分类号： H01L23/48 ,  H01L25/10 ,  H01L23/31 ,  H01L25/065 ,  H01L25/18

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06135 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00012 ,  H01L2924/00

摘要： A package-on-package device includes memory chips side-by-side on a package substrate. Accordingly, it is possible to reduce a thickness of a semiconductor package. Further, data and command pads of a logic chip may be located to be adjacent to data and command pads of the memory chips. Accordingly, a routing distance between pads can be contracted and thus signal delivery speed can be improved. This makes it possible to improve an operation speed of the device.

摘要翻译： 包装封装器件在封装衬底上并排地包括存储器芯片。 因此，可以减小半导体封装的厚度。 此外，逻辑芯片的数据和指令板可以被定位成与存储器芯片的数据和指令焊盘相邻。 因此，焊盘之间的布线距离可以缩小，因此可以提高信号传送速度。 这使得可以提高装置的操作速度。

公开(公告)号：US20130315004A1

公开(公告)日：2013-11-28

申请号：US13833740

申请日：2013-03-15

申请人： Yong Gyu Chu ,  Hyo Soon Kang ,  Seung Bum KO ,  Sang Jae Rhee

发明人： Yong Gyu Chu ,  Hyo Soon Kang ,  Seung Bum KO ,  Sang Jae Rhee

IPC分类号： G11C7/10 ,  H01L23/48 ,  H01L21/50

CPC分类号： G11C7/10 ,  G11C7/1012 ,  G11C7/1045 ,  G11C7/22 ,  G11C2207/105 ,  H01L21/50 ,  H01L23/48 ,  H01L23/50 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/06155 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2225/0651 ,  H01L2924/1434

摘要： A semiconductor device includes a memory cell array, pad groups, a first option pad, a second option pad and a data input multiplexer block configured to transmit data, input through all or part of the pad groups, to the memory cell array based on whether the first option pad and a ground are connected to each other, wherein the data input multiplexer block is configured to select first pad groups among the pad groups or second pad groups among the pad groups as the part of the pad groups based on whether the second option pad and the ground are connected to each other.

摘要翻译： 半导体器件包括存储单元阵列，焊盘组，第一可选焊盘，第二可选焊盘和数据输入多路复用器块，其被配置为基于是否通过全部或部分焊盘组输入数据到存储器单元阵列 所述第一可选焊盘和接地彼此连接，其中所述数据输入多路复用器块被配置为基于所述焊盘组中的所述第二焊盘组或所述焊盘组中的第二焊盘组作为所述焊盘组的一部分来选择所述焊盘组中的第一焊盘组， 选项板和地面相互连接。

公开(公告)号：US09355976B2

公开(公告)日：2016-05-31

申请号：US14077133

申请日：2013-11-11

申请人： Yonghoon Kim ,  Hyo-Soon Kang

发明人： Yonghoon Kim ,  Hyo-Soon Kang

IPC分类号： H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/10 ,  H01L25/18 ,  H01L23/498 ,  H01L23/538

CPC分类号： H01L24/06 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/06135 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

摘要： Provided are semiconductor memory chips and semiconductor packages with the same. The semiconductor package may include a memory chip including first data pads and first command/address pads arranged adjacent to a first side region thereof and second data pads and second command/address pads arranged adjacent to a second side region thereof arranged opposite to the first side region, and a package substrate including first CA connection pads and second CA connection pads. The memory chip may be mounted on a top surface of the package substrate, the first CA connection pads may be connected to the first command/address pads, and the second CA connection pads may be provide to be opposite to the first CA connection pads and be connected to the second command/address pads.

摘要翻译： 提供了具有相同的半导体存储器芯片和半导体封装。 半导体封装可以包括存储器芯片，其包括第一数据焊盘和与其第一侧区域相邻布置的第一命令/地址焊盘以及与其第一侧相对布置的第二侧区域相邻布置的第二数据焊盘和第二命令/地址焊盘 以及包括第一CA连接焊盘和第二CA连接焊盘的封装衬底。 存储器芯片可以安装在封装衬底的顶表面上，第一CA连接焊盘可以连接到第一命令/地址焊盘，并且第二CA连接焊盘可以被提供为与第一CA连接焊盘相对， 连接到第二个命令/地址栏。

公开(公告)号：US20140138851A1

公开(公告)日：2014-05-22

申请号：US14077133

申请日：2013-11-11

申请人： YONGHOON KIM ,  HYO-SOON KANG

发明人： YONGHOON KIM ,  HYO-SOON KANG

IPC分类号： H01L23/00 ,  H01L25/065

CPC分类号： H01L24/06 ,  H01L23/49816 ,  H01L23/5386 ,  H01L24/73 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/02166 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/05571 ,  H01L2224/06135 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1434 ,  H01L2924/15174 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/05552

摘要： Provided are semiconductor memory chips and semiconductor packages with the same. The semiconductor package may include a memory chip including first data pads and first command/address pads arranged adjacent to a first side region thereof and second data pads and second command/address pads arranged adjacent to a second side region thereof arranged opposite to the first side region, and a package substrate including first CA connection pads and second CA connection pads. The memory chip may be mounted on a top surface of the package substrate, the first CA connection pads may be connected to the first command/address pads, and the second CA connection pads may be provide to be opposite to the first CA connection pads and be connected to the second command/address pads.

摘要翻译： 提供了具有相同的半导体存储器芯片和半导体封装。 半导体封装可以包括存储器芯片，其包括第一数据焊盘和与其第一侧区域相邻布置的第一命令/地址焊盘以及与其第一侧相对布置的第二侧区域相邻布置的第二数据焊盘和第二命令/地址焊盘 以及包括第一CA连接焊盘和第二CA连接焊盘的封装衬底。 存储器芯片可以安装在封装衬底的顶表面上，第一CA连接焊盘可以连接到第一命令/地址焊盘，并且第二CA连接焊盘可以被提供为与第一CA连接焊盘相对， 连接到第二个命令/地址栏。

公开(公告)号：US08791559B2

公开(公告)日：2014-07-29

申请号：US13604301

申请日：2012-09-05

申请人： Yong-hoon Kim ,  Hyo-soon Kang ,  Jin-kyung Kim

发明人： Yong-hoon Kim ,  Hyo-soon Kang ,  Jin-kyung Kim

IPC分类号： H01L23/02 ,  H01L23/48 ,  H01L21/50

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0557 ,  H01L2224/06155 ,  H01L2224/06181 ,  H01L2224/1301 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17517 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/14361 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

摘要： A semiconductor package of a package on package structure reducing an overall thickness of the package and simplifying design complexity of wiring paths is provided. The package includes a first package including a first substrate and a first semiconductor chip portion mounted thereon, a second package disposed on the first package and including a second substrate and a second semiconductor chip portion mounted thereon, and a connection member connecting the first and second substrates. The second semiconductor chip portion includes at least one semiconductor chip including a group of chip pads corresponding to one channel, and the group of chip pads is concentrated on a first edge of the semiconductor chip. An intellectual property core corresponding to the one channel is formed on an edge of the first semiconductor chip portion and the IP core corresponds to the edge on which the group of chip pads is concentrated.

摘要翻译： 提供了一种封装结构封装的半导体封装，减少了封装的整体厚度，并简化了布线路径的设计复杂性。 所述封装包括：第一封装，包括第一基板和安装在其上的第一半导体芯片部分;第二封装，设置在所述第一封装上，并且包括第二基板和安装在其上的第二半导体芯片部分;以及连接部件， 底物。 第二半导体芯片部分包括至少一个半导体芯片，其包括对应于一个通道的一组芯片焊盘，并且该组芯片焊盘集中在半导体芯片的第一边缘上。 对应于一个通道的知识产权核心形成在第一半导体芯片部分的边缘上，并且IP核心对应于芯片组集中的边缘。

公开(公告)号：US09466593B2

公开(公告)日：2016-10-11

申请号：US14983510

申请日：2015-12-29

申请人： Dae-Ho Lee ,  Hyo-Soon Kang ,  Seok-Hong Kwon ,  Tae-Young Yoon ,  Hee-Jin Lee

发明人： Dae-Ho Lee ,  Hyo-Soon Kang ,  Seok-Hong Kwon ,  Tae-Young Yoon ,  Hee-Jin Lee

IPC分类号： H01L23/02 ,  H01L25/16 ,  H01L25/10 ,  H01L25/065

CPC分类号： H01L25/162 ,  H01L23/3128 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： A stack semiconductor package includes a first semiconductor package having a first package substrate and a first semiconductor chip mounted on the first package substrate. The first semiconductor chip includes first chip pads arranged along a side portion thereof. The stack semiconductor package includes a second semiconductor package disposed on the first semiconductor package, and includes a second package substrate. A first sub-chip and a second sub-chip is mounted on the second semiconductor package and arranged side by side extending along a direction of a first side portion of the second package substrate. Each of the first and second sub-chips includes second chip pads arranged along a side portion thereof. Connection wiring paths between interface portions and connection pads may be reduced and simplified, thereby preventing connection wires from being tangled. Moreover, connection wiring paths between a logic chip and a memory chip may be minimized, thereby providing high speed performance.

摘要翻译： 堆叠半导体封装包括具有第一封装衬底和安装在第一封装衬底上的第一半导体芯片的第一半导体封装。 第一半导体芯片包括沿其侧部布置的第一芯片焊盘。 堆叠半导体封装包括设置在第一半导体封装上的第二半导体封装，并且包括第二封装衬底。 第一子芯片和第二子芯片安装在第二半导体封装上并且沿着第二封装衬底的第一侧部分的方向并排布置。 第一和第二子芯片中的每一个包括沿着其侧部布置的第二芯片焊盘。 可以减少和简化接口部分和连接焊盘之间的连接布线路径，从而防止连接线缠结。 此外，逻辑芯片和存储芯片之间的连接布线路径可以最小化，从而提供高速性能。

公开(公告)号：US20140217586A1

公开(公告)日：2014-08-07

申请号：US14047120

申请日：2013-10-07

申请人： Yonghoon KIM ,  Hyo-Soon KANG ,  Inho CHOI

发明人： Yonghoon KIM ,  Hyo-Soon KANG ,  Inho CHOI

IPC分类号： H01L25/065 ,  H01L23/00

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L24/73 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/06135 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06565 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/15192 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00012 ,  H01L2924/00

摘要： A package-on-package device includes memory chips side-by-side on a package substrate. Accordingly, it is possible to reduce a thickness of a semiconductor package. Further, data and command pads of a logic chip may be located to be adjacent to data and command pads of the memory chips. Accordingly, a routing distance between pads can be contracted and thus signal delivery speed can be improved. This makes it possible to improve an operation speed of the device.

摘要翻译： 包装封装器件在封装衬底上并排地包括存储器芯片。 因此，可以减小半导体封装的厚度。 此外，逻辑芯片的数据和指令板可以被定位成与存储器芯片的数据和指令焊盘相邻。 因此，焊盘之间的布线距离可以缩小，因此可以提高信号传送速度。 这使得可以提高装置的操作速度。

公开(公告)号：US20130168871A1

公开(公告)日：2013-07-04

申请号：US13604301

申请日：2012-09-05

申请人： Yong-hoon KIM ,  Hyo-soon KANG ,  Jin-kyung KIM

发明人： Yong-hoon KIM ,  Hyo-soon KANG ,  Jin-kyung KIM

IPC分类号： H01L23/48

CPC分类号： H01L25/105 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0657 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05554 ,  H01L2224/0557 ,  H01L2224/06155 ,  H01L2224/06181 ,  H01L2224/1301 ,  H01L2224/13111 ,  H01L2224/13124 ,  H01L2224/13139 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/14181 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/17517 ,  H01L2224/2929 ,  H01L2224/29387 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06562 ,  H01L2225/06565 ,  H01L2225/06575 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/10253 ,  H01L2924/12042 ,  H01L2924/1431 ,  H01L2924/1433 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/14361 ,  H01L2924/1437 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/157 ,  H01L2924/15788 ,  H01L2924/1579 ,  H01L2924/18161 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2924/00

摘要： A semiconductor package of a package on package structure reducing an overall thickness of the package and simplifying design complexity of wiring paths is provided. The package includes a first package including a first substrate and a first semiconductor chip portion mounted thereon, a second package disposed on the first package and including a second substrate and a second semiconductor chip portion mounted thereon, and a connection member connecting the first and second substrates. The second semiconductor chip portion includes at least one semiconductor chip including a group of chip pads corresponding to one channel, and the group of chip pads is concentrated on a first edge of the semiconductor chip. An intellectual property core corresponding to the one channel is formed on an edge of the first semiconductor chip portion and the IP core corresponds to the edge on which the group of chip pads is concentrated.

摘要翻译： 提供了一种封装结构封装的半导体封装，减少了封装的整体厚度，并简化了布线路径的设计复杂性。 所述封装包括：第一封装，包括第一基板和安装在其上的第一半导体芯片部分;第二封装，设置在所述第一封装上，并且包括第二基板和安装在其上的第二半导体芯片部分;以及连接部件， 底物。 第二半导体芯片部分包括至少一个半导体芯片，其包括对应于一个通道的一组芯片焊盘，并且该组芯片焊盘集中在半导体芯片的第一边缘上。 对应于一个通道的知识产权核心形成在第一半导体芯片部分的边缘上，并且IP核心对应于芯片组集中的边缘。

公开(公告)号：US20160190109A1

公开(公告)日：2016-06-30

申请号：US14983510

申请日：2015-12-29

申请人： Dae-Ho Lee ,  Hyo-Soon Kang ,  Seok-Hong Kwon ,  Tae-Young Yoon ,  Hee-Jin Lee

发明人： Dae-Ho Lee ,  Hyo-Soon Kang ,  Seok-Hong Kwon ,  Tae-Young Yoon ,  Hee-Jin Lee

IPC分类号： H01L25/16 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L25/162 ,  H01L23/3128 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： A stack semiconductor package includes a first semiconductor package having a first package substrate and a first semiconductor chip mounted on the first package substrate. The first semiconductor chip includes first chip pads arranged along a side portion thereof. The stack semiconductor package includes a second semiconductor package disposed on the first semiconductor package, and includes a second package substrate. A first sub-chip and a second sub-chip is mounted on the second semiconductor package and arranged side by side extending along a direction of a first side portion of the second package substrate. Each of the first and second sub-chips includes second chip pads arranged along a side portion thereof. Connection wiring paths between interface portions and connection pads may be reduced and simplified, thereby preventing connection wires from being tangled. Moreover, connection wiring paths between a logic chip and a memory chip may be minimized, thereby providing high speed performance.

摘要翻译： 堆叠半导体封装包括具有第一封装衬底和安装在第一封装衬底上的第一半导体芯片的第一半导体封装。 第一半导体芯片包括沿其侧部布置的第一芯片焊盘。 堆叠半导体封装包括设置在第一半导体封装上的第二半导体封装，并且包括第二封装衬底。 第一子芯片和第二子芯片安装在第二半导体封装上并且沿着第二封装衬底的第一侧部分的方向并排布置。 第一和第二子芯片中的每一个包括沿着其侧部布置的第二芯片焊盘。 可以减少和简化接口部分和连接焊盘之间的连接布线路径，从而防止连接线缠结。 此外，逻辑芯片和存储芯片之间的连接布线路径可以最小化，从而提供高速性能。