公开(公告)号：US20160190109A1

公开(公告)日：2016-06-30

申请号：US14983510

申请日：2015-12-29

申请人： Dae-Ho Lee ,  Hyo-Soon Kang ,  Seok-Hong Kwon ,  Tae-Young Yoon ,  Hee-Jin Lee

发明人： Dae-Ho Lee ,  Hyo-Soon Kang ,  Seok-Hong Kwon ,  Tae-Young Yoon ,  Hee-Jin Lee

IPC分类号： H01L25/16 ,  H01L25/065 ,  H01L25/10

CPC分类号： H01L25/162 ,  H01L23/3128 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： A stack semiconductor package includes a first semiconductor package having a first package substrate and a first semiconductor chip mounted on the first package substrate. The first semiconductor chip includes first chip pads arranged along a side portion thereof. The stack semiconductor package includes a second semiconductor package disposed on the first semiconductor package, and includes a second package substrate. A first sub-chip and a second sub-chip is mounted on the second semiconductor package and arranged side by side extending along a direction of a first side portion of the second package substrate. Each of the first and second sub-chips includes second chip pads arranged along a side portion thereof. Connection wiring paths between interface portions and connection pads may be reduced and simplified, thereby preventing connection wires from being tangled. Moreover, connection wiring paths between a logic chip and a memory chip may be minimized, thereby providing high speed performance.

摘要翻译： 堆叠半导体封装包括具有第一封装衬底和安装在第一封装衬底上的第一半导体芯片的第一半导体封装。 第一半导体芯片包括沿其侧部布置的第一芯片焊盘。 堆叠半导体封装包括设置在第一半导体封装上的第二半导体封装，并且包括第二封装衬底。 第一子芯片和第二子芯片安装在第二半导体封装上并且沿着第二封装衬底的第一侧部分的方向并排布置。 第一和第二子芯片中的每一个包括沿着其侧部布置的第二芯片焊盘。 可以减少和简化接口部分和连接焊盘之间的连接布线路径，从而防止连接线缠结。 此外，逻辑芯片和存储芯片之间的连接布线路径可以最小化，从而提供高速性能。

公开(公告)号：US09466593B2

公开(公告)日：2016-10-11

申请号：US14983510

申请日：2015-12-29

申请人： Dae-Ho Lee ,  Hyo-Soon Kang ,  Seok-Hong Kwon ,  Tae-Young Yoon ,  Hee-Jin Lee

发明人： Dae-Ho Lee ,  Hyo-Soon Kang ,  Seok-Hong Kwon ,  Tae-Young Yoon ,  Hee-Jin Lee

IPC分类号： H01L23/02 ,  H01L25/16 ,  H01L25/10 ,  H01L25/065

CPC分类号： H01L25/162 ,  H01L23/3128 ,  H01L24/06 ,  H01L24/13 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/92 ,  H01L25/0652 ,  H01L25/0655 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05553 ,  H01L2224/06135 ,  H01L2224/131 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/92125 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/1436 ,  H01L2924/15192 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/014 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00

摘要： A stack semiconductor package includes a first semiconductor package having a first package substrate and a first semiconductor chip mounted on the first package substrate. The first semiconductor chip includes first chip pads arranged along a side portion thereof. The stack semiconductor package includes a second semiconductor package disposed on the first semiconductor package, and includes a second package substrate. A first sub-chip and a second sub-chip is mounted on the second semiconductor package and arranged side by side extending along a direction of a first side portion of the second package substrate. Each of the first and second sub-chips includes second chip pads arranged along a side portion thereof. Connection wiring paths between interface portions and connection pads may be reduced and simplified, thereby preventing connection wires from being tangled. Moreover, connection wiring paths between a logic chip and a memory chip may be minimized, thereby providing high speed performance.

摘要翻译： 堆叠半导体封装包括具有第一封装衬底和安装在第一封装衬底上的第一半导体芯片的第一半导体封装。 第一半导体芯片包括沿其侧部布置的第一芯片焊盘。 堆叠半导体封装包括设置在第一半导体封装上的第二半导体封装，并且包括第二封装衬底。 第一子芯片和第二子芯片安装在第二半导体封装上并且沿着第二封装衬底的第一侧部分的方向并排布置。 第一和第二子芯片中的每一个包括沿着其侧部布置的第二芯片焊盘。 可以减少和简化接口部分和连接焊盘之间的连接布线路径，从而防止连接线缠结。 此外，逻辑芯片和存储芯片之间的连接布线路径可以最小化，从而提供高速性能。