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    Nonvolatile memory structures and access methods
    1.
    发明授权
    Nonvolatile memory structures and access methods 有权

    公开(公告)号：US06584018B2

    公开(公告)日：2003-06-24

    申请号：US09972388

    申请日：2001-10-05

    Applicant: Hsing T. Tuan ,  Li-Chun Li ,  Vei-Han Chan

    Inventor： Hsing T. Tuan ,  Li-Chun Li ,  Vei-Han Chan

    IPC: G11C1134

    CPC classification number: G11C16/08 ,  G11C8/08

    Abstract: In each row of a nonvolatile memory array, the select gates of all the memory cells are connected together and are used to select a row for memory access. The control gates of each row are also connected together, and the source regions of each row are connected together. Also, the control gates of plural rows are connected together, and the source regions of plural rows are connected together, but if the source regions of two rows are connected together, then their control gates are not connected together. If one of the two rows is being accessed but the other one of the two rows is not being accessed, their control gates are driven to different voltages, reducing the probability of a punch-through in the non-accessed row.

    Read-only/read-write memory
    3.
    发明授权
    Read-only/read-write memory 失效
    只读/读写存储器

    公开(公告)号：US4380803A

    公开(公告)日：1983-04-19

    申请号：US233066

    申请日：1981-02-10

    Applicant: Hsing T. Tuan

    Inventor： Hsing T. Tuan

    IPC: G11C14/00 ,  G11C7/20 ,  G11C11/00 ,  G11C11/401 ,  G11C11/404 ,  G11C17/12 ,  H01L21/8242 ,  H01L21/8246 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/112 ,  H01L29/78 ,  G11C7/00

    CPC classification number: G11C7/20 ,  G11C11/005 ,  G11C11/404 ,  G11C17/12 ,  H01L27/108

    Abstract: An improved read-only/read-write semiconductor memory of the type that includes a semiconductor substrate with dopant atoms of a first conductivity type, a pair of spaced-apart charge storage regions at the surface of the substrate, a bit line at the surface of the substrate spaced apart from the charge storage region, respective MOSFET transistor gate regions at the surface of the substrate between the bit line and the charge storage regions, and a conductor over the storage regions; the improvement comprising dopant atoms of a second conductivity type in one of the storage regions, and dopant atoms of the first conductivity type in the other of the storage regions having a greater doping concentration than is in the body of the substrate; and circuitry for applying a read-write mode voltage to the conductor to permit charge to be stored in both of the storage regions, and for applying a read-only mode voltage to the conductor to permit charge to be stored in the one storage region and simultaneously prevent charge from being stored in the other storage region by there producing a potential barrier.

    Abstract translation: 一种改进的只读/读写半导体存储器，其包括具有第一导电类型的掺杂剂原子的半导体衬底，在衬底的表面处的一对间隔电荷存储区域，在表面处的位线 与位于电荷存储区之间的基板表面上的各个MOSFET晶体管栅极区域和存储区域上的导体; 所述改进包括在一个存储区域中的第二导电类型的掺杂剂原子，并且在另一个存储区域中的第一导电类型的掺杂剂原子具有比衬底的体内更大的掺杂浓度; 以及用于向导体施加读写模式电压以允许电荷存储在两个存储区域中的电路，以及用于向导体施加只读模式电压以允许电荷存储在一个存储区域中，以及 同时通过产生潜在的屏障来防止电荷存储在另一个存储区域中。

    Integrated circuit memory with decoded address sustain circuitry for multiplexed address architecture and method
    5.
    发明授权
    Integrated circuit memory with decoded address sustain circuitry for multiplexed address architecture and method 失效
    具有用于复用地址架构和方法的解码地址维持电路的集成电路存储器

    公开(公告)号：US5245583A

    公开(公告)日：1993-09-14

    申请号：US679511

    申请日：1991-04-02

    Applicant: Li-Chun Li ,  Hsing T. Tuan ,  Lynne Hannah

    Inventor： Li-Chun Li ,  Hsing T. Tuan ,  Lynne Hannah

    IPC: G11C8/10 ,  G11C11/408

    CPC classification number: G11C8/10 ,  G11C11/4087

    Abstract: An integrated circuit memory device is provided which includes a memory array including multiple memory cores, each core including a two-dimensional (x,y) array of memory cells, the memory array further including a plurality of x-lines and a plurality of y-lines; an address bus including a first bus oriented with a y-dimension and a second bus oriented with an x-dimension; and x-address generator; a y-address generator; a multiplexer circuit for operatively coupling one of the x-address generator and the y-address generator to the address bus; a plurality of y-address decoders each for producing decoded y-information to at least one of the plurality of y-lines; a plurality of separate x-address decoders each for producing decoded x-information for at least one of the plurality of x-lines; and a plurality of separate sustain circuits each for sustaining decoded x-information produced by at least one x-decoder.

    Abstract translation: 提供一种集成电路存储器件，其包括包括多个存储器核的存储器阵列，每个核心包括存储器单元的二维（x，y）阵列，所述存储器阵列还包括多个x线和多个y 线条 一个地址总线，包括一个以y维取向的第一总线和一个以x维取向的第二总线; 和x地址发生器; 一个y地址生成器; 用于将所述x地址发生器和所述y地址发生器中的一个可操作地耦合到所述地址总线的多路复用器电路; 多个y地址解码器，用于将解码的y信息产生到多个y行中的至少一个; 多个单独的x地址解码器，用于产生所述多个x行中的至少一个的解码的x信息; 以及多个单独的维持电路，用于维持由至少一个x解码器产生的解码的x信息。

    Nonvolatile memory structures and access methods
    6.
    发明授权
    Nonvolatile memory structures and access methods 有权
    非易失性存储器结构和访问方法

    公开(公告)号：US06674669B2

    公开(公告)日：2004-01-06

    申请号：US10268863

    申请日：2002-10-09

    Applicant: Hsing T. Tuan ,  Li-Chun Li ,  Vei-Han Chan

    Inventor： Hsing T. Tuan ,  Li-Chun Li ,  Vei-Han Chan

    IPC: G11C1134

    CPC classification number: G11C16/08 ,  G11C8/08

    Abstract: In each row of a nonvolatile memory array, the select gates of all the memory cells are connected together and are used to select a row for memory access. The control gates of each row are also connected together, and the source regions of each row are connected together. Also, the control gates of plural rows are connected together, and the source regions of plural rows are connected together, but if the source regions of two rows are connected together, then their control gates are not connected together. If one of the two rows is being accessed but the other one of the two rows is not being accessed, their control gates are driven to different voltages, reducing the probability of a punch-through in the non-accessed row.

    Abstract translation: 在非易失性存储器阵列的每行中，所有存储器单元的选择栅极连接在一起，并用于选择用于存储器存取的行。 每行的控制栅极也连接在一起，并且每行的源极区域连接在一起。 此外，多行的控制栅极连接在一起，并且多行的源极区域连接在一起，但是如果两行的源极区域连接在一起，则它们的控制栅极不连接在一起。 如果两行中的一个被访问，但是两行中的另一行未被访问，则它们的控制栅极被驱动到不同的电压，从而降低在未访问行中穿透的可能性。

    Charge restore circuit for semiconductor memories
    8.
    发明授权
    Charge restore circuit for semiconductor memories 失效
    半导体存储器的电荷恢复电路

    公开(公告)号：US4262342A

    公开(公告)日：1981-04-14

    申请号：US53084

    申请日：1979-06-28

    Applicant: Hsing T. Tuan

    Inventor： Hsing T. Tuan

    IPC: G11C11/404 ,  G11C11/4094 ,  G11C7/00

    CPC classification number: G11C11/404 ,  G11C11/4094

    Abstract: Disclosed is a circuit for restoring charge to the cells of a semiconductor memory during a read operation. A respective one of the circuits couples to each of the bit lines of the memory. No power is dissipated in those circuits which couple the bit lines that are to be discharged during a read. Also, the circuit includes only three transistors, and thus occupies a minimal amount of chip space. In addition, the circuit is operable in response to only a single clocking signal. Further, the circuit is operable over a relatively large range of precharge voltage levels for the bit lines such as 3 volts to 7 volts.

    Abstract translation: 公开了一种用于在读取操作期间将电荷恢复到半导体存储器的单元的电路。 电路中的相应一个耦合到存储器的每个位线。 在读取期间将要排出的位线的那些电路中的电路中没有功率消耗。 此外，电路仅包括三个晶体管，因此占用最小量的芯片空间。 此外，电路仅响应于单个时钟信号而可操作。 此外，该电路可在诸如3伏至7伏的位线的相对较大的预充电电压电平范围内操作。

    Ram having a stabilized substrate bias and low-threshold narrow-width transfer gates
    9.
    发明授权
    Ram having a stabilized substrate bias and low-threshold narrow-width transfer gates 失效
    Ram具有稳定的衬底偏置和低阈值窄宽度传输门

    公开(公告)号：US4262298A

    公开(公告)日：1981-04-14

    申请号：US72446

    申请日：1979-09-04

    Applicant: Hsing T. Tuan ,  Donald L. Henderson, Sr. ,  Robert N. Ruth, Jr.

    Inventor： Hsing T. Tuan ,  Donald L. Henderson, Sr. ,  Robert N. Ruth, Jr.

    IPC: G11C11/34 ,  G05F3/20 ,  G11C11/404 ,  G11C11/4076 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L29/78 ,  H01L27/02

    CPC classification number: G05F3/205 ,  G11C11/404 ,  G11C11/4076 ,  H01L27/10805

    Abstract: Disclosed is a RAM that includes a semiconductor substrate having P-type dopant impurity atoms and having a major surface. A plurality of spaced apart regions of N-type atoms lie within a predetermined area on the surface to define storage regions for the cells of the memory. An insulating layer of substantially uniform thickness with a conductive layer lying thereon completely covers the predetermined area except for a plurality of elongated openings which extend outward from each of the storage regions. A layer of P-type dopant atoms lie at substantially the same level as the storage regions throughout that portion of the substrate that is beneath the insulating layer. By this structure, the perimeter of a transfer gate that exhibits essentially no narrow channel width effect is defined from each storage region by the respective openings. Also, a capacitor for stabilizing the bias voltage of the substrate is formed by the combination of that portion of the insulating layer and conductive layer which lies between the storage regions.

    Abstract translation: 公开了一种RAM，其包括具有P型掺杂剂杂质原子并具有主表面的半导体衬底。 N型原子的多个间隔开的区域位于表面上的预定区域内，以限定存储器单元的存储区域。 具有基本上均匀厚度的绝缘层，其上具有导电层完全覆盖预定区域，除了从每个存储区域向外延伸的多个细长开口。 一层P型掺杂剂原子处于与绝缘层下面的衬底的该部分的存储区域基本相同的水平。 通过这种结构，通过相应的开口从每个存储区域确定表现出基本上不窄的沟道宽度效应的传输门的周边。 此外，用于稳定衬底的偏置电压的电容器通过绝缘层和位于存储区域之间的导电层的那部分的组合形成。

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