公开(公告)号：US07897659B2

公开(公告)日：2011-03-01

申请号：US12358248

申请日：2009-01-23

Applicant: Chung Wai Leung

Inventor： Chung Wai Leung

IPC: C08J9/32

CPC classification number: C08K5/1545 ,  C08K7/22 ,  C08L29/04 ,  C08L31/04

Abstract: A water-based moldable modeling dough includes polyvinyl alcohol (PVA), vinyl acetate resin, water, maltose, maltitol, and hollow microspheres each with a diameter about 5-100 μm.

Abstract translation: 水性可成型造型面团包括直径约5-100μm的聚乙烯醇（PVA），乙酸乙烯酯树脂，水，麦芽糖，麦芽糖醇和中空微球。

公开(公告)号：US06700143B2

公开(公告)日：2004-03-02

申请号：US10165741

申请日：2002-06-06

Applicant: Hsing Ti Tuan ,  Chung Wai Leung

Inventor： Hsing Ti Tuan ,  Chung Wai Leung

IPC: H01L31119

CPC classification number: H01L27/11526 ,  H01L21/31053 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546 ,  Y10S438/926

Abstract: Circuit elements (e.g. transistor gates) formed over a semiconductor substrate are protected by adjacent dummy structures during mechanical or chemical mechanical polishing of an overlying dielectric.

Abstract translation: 形成在半导体衬底上的电路元件（例如晶体管栅极）在上覆电介质的机械或化学机械抛光期间被相邻的虚设结构保护。

公开(公告)号：US06821847B2

公开(公告)日：2004-11-23

申请号：US09969841

申请日：2001-10-02

Applicant: Chung Wai Leung ,  Chia-Shun Hsiao ,  Vei-Han Chan

Inventor： Chung Wai Leung ,  Chia-Shun Hsiao ,  Vei-Han Chan

IPC: H01L218247

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control gates overlie the floating gates. Each pair of the first structures corresponds to a plurality of doped regions each of which provides a source/drain region to a memory cell having the floating and control gates in one or the structure and a source/drain region to a memory cell having floating and control gates in the other one of the structures. For each pair, a second conductive line is formed whose bottom surface extends between the two structures and physically contacts the corresponding first doped regions. In some embodiments, the first doped regions are separated by insulation trenches. The second conductive line may form a conductive plug at least partially filling the region between the two first structures.

公开(公告)号：US06815760B2

公开(公告)日：2004-11-09

申请号：US10200443

申请日：2002-07-22

Applicant: Chung Wai Leung ,  Chia-Shun Hsiao ,  Vei-Han Chan

Inventor： Chung Wai Leung ,  Chia-Shun Hsiao ,  Vei-Han Chan

IPC: H01L29788

CPC classification number: H01L27/11521 ,  H01L27/115

Abstract: To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control gates overlie the floating gates. Each pair of the first structures corresponds to a plurality of doped regions each of which provides a source/drain region to a memory cell having the floating and control gates in one or the structure and a source/drain region to a memory cell having floating and control gates in the other one of the structures. For each pair, a second conductive line is formed whose bottom surface extends between the two structures and physically contacts the corresponding first doped regions. In some embodiments, the first doped regions are separated by insulation trenches. The second conductive line may form a conductive plug at least partially filling the region between the two first structures.

公开(公告)号：US06570215B2

公开(公告)日：2003-05-27

申请号：US10199157

申请日：2002-07-18

Applicant: Hsing T. Tuan ,  Vei-Han Chan ,  Chung Wai Leung ,  Chia-Shun Hsiao

Inventor： Hsing T. Tuan ,  Vei-Han Chan ,  Chung Wai Leung ,  Chia-Shun Hsiao

IPC: H01L2362

CPC classification number: H01L27/11521 ,  H01L21/28273 ,  H01L27/115 ,  H01L29/42324 ,  H01L29/42328 ,  H01L29/42336

Abstract: In a nonvolatile memory, a floating gate includes a portion of a conductive layer (150), and also includes conductive spacers (610). The spacers increase the capacitive coupling between the floating gate and the control gate (170).

公开(公告)号：US06559055B2

公开(公告)日：2003-05-06

申请号：US09846123

申请日：2001-04-30

Applicant: Hsing Ti Tuan ,  Chung Wai Leung

Inventor： Hsing Ti Tuan ,  Chung Wai Leung

IPC: H01L21336

CPC classification number: H01L27/11526 ,  H01L21/31053 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546 ,  Y10S438/926

Abstract: Circuit elements (e.g. transistor gates) formed over a semiconductor substrate are protected by adjacent dummy structures during mechanical or chemical mechanical polishing of an overlying dielectric.

公开(公告)号：US06355524B1

公开(公告)日：2002-03-12

申请号：US09640139

申请日：2000-08-15

Applicant: Hsing Ti Tuan ,  Li-Chun Li ,  Chung Wai Leung ,  Thomas Tong-Long Chang

Inventor： Hsing Ti Tuan ,  Li-Chun Li ,  Chung Wai Leung ,  Thomas Tong-Long Chang

IPC: H01L21336

CPC classification number: H01L27/11526 ,  H01L21/31053 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11546

Abstract: In a nonvolatile memory, select gates are self-aligned spacers formed on sidewalls of floating/control gate stacks. The same mask (1710) is used to remove the select gate layer from over the source lines (144), to etch trench insulation in the source line regions, and to dope the source lines. The memory can be formed in and over an isolated substrate region. The source lines can be doped at least partially before the trench insulation is etched, to prevent a short before the source lines and a region isolating the isolated substrate region from below. The memory can be erased by sectors, or alternatively a chip erase operation can be performed to erase all the cells in parallel. Peripheral transistor gates can be formed from the same layer as the select gates. The select gate spacers have extensions to which low resistance contacts can be made from overlying metal lines.

公开(公告)号：US06313500B1

公开(公告)日：2001-11-06

申请号：US09460812

申请日：1999-12-14

Applicant: Patrick J. Kelley ,  Chung Wai Leung ,  Ranbir Singh

Inventor： Patrick J. Kelley ,  Chung Wai Leung ,  Ranbir Singh

IPC: H01L29788

CPC classification number: H01L21/28273 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7885

Abstract: A split gate memory cell is described which is fabricated from two-polysilicon layers and comprises a silicon substrate having a source and a drain electrode and a storage node, a tunnel oxide on the substrate, a first control gate electrode and a floating gate electrode spaced from each other and fabricated from the same polysilicon layer and a second control gate electrode of a second poly material formed between and over the first control gate and floating gate and isolated therefrom by a dielectric layer therebetween.

Abstract translation: 描述了由双多晶硅层制造并包括具有源极和漏极和存储节点的硅衬底，衬底上的隧道氧化物，间隔开的第一控制栅电极和浮栅电极的分离栅极存储单元 彼此之间并由第一多个控制栅极和浮置栅极之间形成的第二多晶硅层的同一多晶硅层和第二控制栅电极制成，并通过第一控制栅极和浮栅之间的介电层与其隔离。

公开(公告)号：US5851870A

公开(公告)日：1998-12-22

申请号：US644086

申请日：1996-05-09

Applicant: Dayo Alugbin ,  Chung Wai Leung ,  Joseph Rudolph Radosevich ,  Ranbir Singh ,  Daniel Mark Wroge

Inventor： Dayo Alugbin ,  Chung Wai Leung ,  Joseph Rudolph Radosevich ,  Ranbir Singh ,  Daniel Mark Wroge

IPC: H01G4/10 ,  H01L21/02 ,  H01L21/822 ,  H01L27/04 ,  H01L21/8242

CPC classification number: H01L28/40 ,  Y10S148/014

Abstract: A novel capacitor design for use in semiconductor integrated circuits is disclosed. The capacitor includes a metal-dielectric-metal stack formed within a window and upon a conductive substrate. Contact to the top plate of the capacitor is through a window within a window, while contact to the bottom plate is achieved by a guard ring which contacts the conductive substrate.

Abstract translation: 公开了一种用于半导体集成电路的新型电容器设计。 该电容器包括形成在窗口内和导电基底上的金属 - 介电金属叠层。 与电容器的顶板的接触是通过窗内的窗口，而与底板的接触通过接触导电基板的保护环来实现。

公开(公告)号：US06566196B1

公开(公告)日：2003-05-20

申请号：US10146979

申请日：2002-05-15

Applicant: Barbara Haselden ,  Chia-Shun Hsiao ,  Chunchieh Huang ,  Jin-Ho Kim ,  Chung Wai Leung ,  Kuei-Chang Tsai

Inventor： Barbara Haselden ,  Chia-Shun Hsiao ,  Chunchieh Huang ,  Jin-Ho Kim ,  Chung Wai Leung ,  Kuei-Chang Tsai

IPC: H01L21336

CPC classification number: H01L27/11521 ,  H01L27/115 ,  H01L29/42324 ,  Y10S438/954

Abstract: In a nonvolatile memory, a floating gate (124) is covered with ONO (98), and a control gate polysilicon layer (124) is formed on the ONO. After the control gate is patterned, the control gate sidewalls are oxidized to form a protective layer (101) of silicon dioxide. This oxide protects the control gate polysilicon during a subsequent etch of the silicon nitride portion (98.2) of the ONO. Therefore, the silicon nitride can be removed with an isotropic etch. A potential damage to the substrate isolation dielectric (210) is therefore reduced. Other embodiments are also provided.

Abstract translation: 在非易失性存储器中，浮动栅极（124）被ONO（98）覆盖，并且在ONO上形成控制栅多晶硅层（124）。 在控制栅极被图案化之后，控制栅极侧壁被氧化以形成二氧化硅的保护层（101）。 该氧化物在ONO的氮化硅部分（98.2）的随后蚀刻期间保护控制栅极多晶硅。 因此，可以用各向同性蚀刻去除氮化硅。 因此，减小了对衬底隔离电介质（210）的潜在损害。 还提供了其他实施例。