公开(公告)号：US5851870A

公开(公告)日：1998-12-22

申请号：US644086

申请日：1996-05-09

Applicant: Dayo Alugbin ,  Chung Wai Leung ,  Joseph Rudolph Radosevich ,  Ranbir Singh ,  Daniel Mark Wroge

Inventor： Dayo Alugbin ,  Chung Wai Leung ,  Joseph Rudolph Radosevich ,  Ranbir Singh ,  Daniel Mark Wroge

IPC: H01G4/10 ,  H01L21/02 ,  H01L21/822 ,  H01L27/04 ,  H01L21/8242

CPC classification number: H01L28/40 ,  Y10S148/014

Abstract: A novel capacitor design for use in semiconductor integrated circuits is disclosed. The capacitor includes a metal-dielectric-metal stack formed within a window and upon a conductive substrate. Contact to the top plate of the capacitor is through a window within a window, while contact to the bottom plate is achieved by a guard ring which contacts the conductive substrate.

Abstract translation: 公开了一种用于半导体集成电路的新型电容器设计。 该电容器包括形成在窗口内和导电基底上的金属 - 介电金属叠层。 与电容器的顶板的接触是通过窗内的窗口，而与底板的接触通过接触导电基板的保护环来实现。

公开(公告)号：US5268332A

公开(公告)日：1993-12-07

申请号：US975235

申请日：1992-11-12

Applicant: Dayo Alugbin ,  Franklin D. Nkansah ,  Kolawole R. Olasupo

Inventor： Dayo Alugbin ,  Franklin D. Nkansah ,  Kolawole R. Olasupo

IPC: C23C14/00 ,  C23F1/00 ,  H01L21/28 ,  H01L21/3205 ,  H01L21/3213 ,  H01L21/768 ,  H01L23/522 ,  H01L21/465

CPC classification number: H01L21/76802

Abstract: A method for forming an integrated circuit with a planarized dielectric is disclosed. Runners and gates are covered with a protective dielectric layer. Then a conventional dielectric is deposited and planarized over the entire circuit surface. When windows are opened to runners and to source/drain regions, the protective dielectric helps to slow the etch process over the runner, thus protecting the runner from damage during the extra time required for the etch process to reach the source or drain.