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    Capacitance multiplier
    2.
    发明授权
    Capacitance multiplier 有权
    电容倍增器

    公开(公告)号：US07113022B2

    公开(公告)日：2006-09-26

    申请号：US10941357

    申请日：2004-09-15

    Applicant: Young-Jin Kim ,  In-Chul Hwang ,  Han-Il Lee ,  Jae-Heon Lee

    Inventor： Young-Jin Kim ,  In-Chul Hwang ,  Han-Il Lee ,  Jae-Heon Lee

    IPC: G05F1/10

    CPC classification number: H03H11/483

    Abstract: A capacitance multiplier includes a self-biasing active load for generating a stable bias voltage without a separate current bias. In addition, the capacitance multiplier includes a cascode load within a multiplying section for increasing the output resistance and in turn the charging/discharging efficiency. Furthermore, the capacitance multiplier is implemented with a plurality of multiplying paths to reduce effects of noise for more stable generation of the multiplied capacitance.

    Abstract translation: 电容倍增器包括用于在没有单独的电流偏置的情况下产生稳定的偏置电压的自偏置有源负载。 此外，电容倍增器包括用于增加输出电阻以及再次充电/放电效率的乘法部分内的共源共栅负载。 此外，电容乘法器用多个乘法路径实现，以减少噪声的影响，以便更多地稳定地产生倍增的电容。

    Capacitance multiplier
    4.
    发明授权
    Capacitance multiplier 有权
    电容倍增器

    公开(公告)号：US07436240B2

    公开(公告)日：2008-10-14

    申请号：US11506034

    申请日：2006-08-17

    Applicant: Young-Jin Kim ,  In-Chul Hwang ,  Han-Il Lee ,  Jae-Heon Lee

    Inventor： Young-Jin Kim ,  In-Chul Hwang ,  Han-Il Lee ,  Jae-Heon Lee

    IPC: G05F1/10

    CPC classification number: H03H11/483

    Abstract: A capacitance multiplier includes a self-biasing active load for generating a stable bias voltage without a separate current bias. In addition, the capacitance multiplier includes a cascode load within a multiplying section for increasing the output resistance and in turn the charging/discharging efficiency. Furthermore, the capacitance multiplier is implemented with a plurality of multiplying paths to reduce effects of noise for more stable generation of the multiplied capacitance.

    Abstract translation: 电容倍增器包括用于在没有单独的电流偏置的情况下产生稳定的偏置电压的自偏置有源负载。 此外，电容倍增器包括用于增加输出电阻以及再次充电/放电效率的乘法部分内的共源共栅负载。 此外，电容乘法器用多个乘法路径实现，以减少噪声的影响，以便更多地稳定地产生倍增的电容。

    Capacitance multiplier
    5.
    发明申请
    Capacitance multiplier 有权
    电容倍增器

    公开(公告)号：US20050099221A1

    公开(公告)日：2005-05-12

    申请号：US10941357

    申请日：2004-09-15

    Applicant: Young-Jin Kim ,  In-Chul Hwang ,  Han-Il Lee ,  Jae-Heon Lee

    Inventor： Young-Jin Kim ,  In-Chul Hwang ,  Han-Il Lee ,  Jae-Heon Lee

    IPC: H03H11/48 ,  G06G7/16

    CPC classification number: H03H11/483

    Abstract: A capacitance multiplier includes a self-biasing active load for generating a stable bias voltage without a separate current bias. In addition, the capacitance multiplier includes a cascode load within a multiplying section for increasing the output resistance and in turn the charging/discharging efficiency. Furthermore, the capacitance multiplier is implemented with a plurality of multiplying paths to reduce effects of noise for more stable generation of the multiplied capacitance.

    Abstract translation: 电容倍增器包括用于在没有单独的电流偏置的情况下产生稳定的偏置电压的自偏置有源负载。 此外，电容倍增器包括用于增加输出电阻以及再次充电/放电效率的乘法部分内的共源共栅负载。 此外，电容乘法器用多个乘法路径实现，以减少噪声的影响，以便更多地稳定地产生倍增的电容。

    Multi-band transceiver for a wireless communication system
    8.
    发明申请
    Multi-band transceiver for a wireless communication system 有权
    用于无线通信系统的多频带收发器

    公开(公告)号：US20050085206A1

    公开(公告)日：2005-04-21

    申请号：US10967386

    申请日：2004-10-18

    Applicant: Han-Il Lee ,  In-chul Hwang

    Inventor： Han-Il Lee ,  In-chul Hwang

    IPC: H03L7/16 ,  H03L7/197 ,  H03L7/23 ,  H04B1/40 ,  H04B1/06 ,  H04B7/00 ,  H04M1/00

    CPC classification number: H03L7/23 ,  H03L7/16 ,  H03L7/1974 ,  H04B1/406

    Abstract: A local oscillation signal generator and a multi-band transceiver including the local oscillation signal generator are provided. The multi-band transceiver includes a fractional-N phased locked loop (PLL), a local oscillation signal generator, and a transmitter. The fractional-N PLL receives a reference signal and outputs an oscillation signal that is phase-locked to the reference signal. The local oscillation signal generator receives the oscillation signal and outputs a first divided signal that is obtained by dividing a frequency of the oscillation signal by a first value and a second divided signal that is obtained by dividing the frequency of the oscillation signal by a second value. The transmitter receives input signals and generates a transmitter signal using an equation f TX = ( 2 3 ⁢ k - 1 M ) ⁢ f VCO , based on the first divided signal and the second divided signal.

    Abstract translation: 提供本地振荡信号发生器和包括本地振荡信号发生器的多频带收发器。 多频带收发器包括分数N相位锁相环（PLL），本地振荡信号发生器和发射机。 分数N PLL接收参考信号，并将相位锁定的振荡信号输出到参考信号。 本地振荡信号发生器接收振荡信号，并输出通过将振荡信号的频率除以第一值而获得的第一分频信号和通过将振荡信号的频率除以第二值获得的第二分频信号 。 发射机接收输入信号并使用公式生成发射机信号 f TX = （ / MN> 3 k MN> 1 VCO 和第二分频信号。

      Frequency synthesizer using a wide-band voltage controlled oscillator and a fast adaptive frequency calibration method
      9.
      发明申请
      Frequency synthesizer using a wide-band voltage controlled oscillator and a fast adaptive frequency calibration method 有权
      使用宽带压控振荡器的频率合成器和快速自适应频率校准方法

      公开(公告)号：US20050083137A1

      公开(公告)日：2005-04-21

      申请号：US10942119

      申请日：2004-09-15

      Applicant: Han-il Lee ,  In-chul Hwang

      Inventor： Han-il Lee ,  In-chul Hwang

      IPC: H03L7/16 ,  H03L7/00 ,  H03L7/085 ,  H03L7/087 ,  H03L7/099 ,  H03L7/10 ,  H03L7/18

      CPC classification number: H03L7/113 ,  H03L7/085 ,  H03L7/087 ,  H03L7/099 ,  H03L7/18

      Abstract: A frequency synthesizer is provided. The frequency synthesizer includes an adaptive frequency calibration circuit and a phase locked loop (PLL). The frequency synthesizer performs in a frequency lock mode and in a phase lock mode. In the frequency lock mode, the adaptive frequency calibration circuit compares the frequency of an input signal with the frequency of an output signal of a voltage controlled oscillator of the PLL and outputs control bits as a result of the comparison. The voltage controlled oscillator has a plurality of operating characteristic curves and selects a curve from among the plurality of operating characteristic curves in response to the control bits. In the phase lock mode, the PLL controls an output phase of the voltage controlled oscillator based on a tuning voltage from the selected operating characteristic curve.

      Abstract translation: 提供频率合成器。 频率合成器包括自适应频率校准电路和锁相环（PLL）。 频率合成器在频率锁定模式和相位锁定模式下执行。 在频率锁定模式中，自适应频率校准电路将输入信号的频率与PLL的压控振荡器的输出信号的频率进行比较，并作为比较结果输出控制位。 压控振荡器具有多个工作特性曲线，并响应于控制位选择多个操作特性曲线中的曲线。 在锁相模式下，PLL根据所选工作特性曲线的调谐电压控制压控振荡器的输出相位。

      Phase-locked loop for reducing frequency lock time
      10.
      发明授权
      Phase-locked loop for reducing frequency lock time 失效

      公开(公告)号：US06512403B2

      公开(公告)日：2003-01-28

      申请号：US10034891

      申请日：2001-12-20

      Applicant: Han-il Lee

      Inventor： Han-il Lee

      IPC: H03K1704

      CPC classification number: H03L7/187 ,  H03L7/0891 ,  H03L7/10

      Abstract: A phase-locked loop circuit includes a phase detector for comparing the phase of a reference clock signal with the phase of a feedback clock signal and detecting a phase difference between the two; a loop filter in signal communication with the phase detector; a fast frequency lock control circuit in signal communication with the phase detector for disconnecting the phase detector from the loop filter at the initial stage of power on of the phase-locked loop circuit, at least one of supplying constant current to the loop filter for a predetermined time duration and emitting constant current from the loop filter, and then connecting the phase detector to the loop filter; a voltage controlled oscillator in signal communication with the loop filter for generating an output clock signal and varying the frequency of the output clock signal in response to output voltage of the loop filter; and a divider in signal communication with the voltage controlled oscillator for dividing the output clock signal at a predetermined division rate and supplying the divided clock signal as the feedback clock signal.

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