公开(公告)号：US06469566B2

公开(公告)日：2002-10-22

申请号：US09773268

申请日：2001-01-31

Applicant: Salvatore Nicosia

Inventor： Salvatore Nicosia

IPC: H03K1704

CPC classification number: G11C7/1057 ,  G11C7/1018 ,  G11C7/1039 ,  G11C7/1042 ,  G11C7/1045 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1069 ,  G11C7/1072 ,  G11C7/22 ,  G11C8/04 ,  G11C8/18

Abstract: A pre-charging circuit for the output node of an output buffer of an integrated digital system generates a first pulse for enabling the output of new data and a second pulse having a shorter duration than the first pulse for loading the new data in an output data register. The output data register is coupled to the input of the output buffer. A capacitor is connected in parallel to the load capacitance of the output node of the buffer by a pass-gate. The pass-gate is enabled by a pre-charge command corresponding to the logic AND of the second pulse and of the logic XOR of the new data and the data currently present on the output node. A driver is disabled by the first pulse for charging the capacitor to a voltage corresponding to the logic level of data belonging to the group that includes the new data and a logic inversion of the current data.

Abstract translation: 用于集成数字系统的输出缓冲器的输出节点的预充电电路产生用于使新数据的输出的第一脉冲和具有比第一脉冲更短的持续时间的第二脉冲，用于将新数据加载到输出数据中 寄存器。 输出数据寄存器耦合到输出缓冲器的输入端。 电容器通过闸门与缓冲器的输出节点的负载电容并联连接。 通过对应于第二脉冲的逻辑AND和新数据的逻辑和和输出节点上当前存在的数据的预充电命令来使能通过门。 通过用于将电容器充电到与属于包括新数据的组的数据的逻辑电平相对应的电压和当前数据的逻辑反相的第一脉冲禁用驱动器。

公开(公告)号：US06377107B1

公开(公告)日：2002-04-23

申请号：US09614432

申请日：2000-07-12

Applicant: Felix Franck

Inventor： Felix Franck

IPC: H03K1704

CPC classification number: H03K17/04213 ,  H02M7/5383 ,  H03K2217/0036

Abstract: A circuit arrangement having at least one electric main switch (T1) with a reference electrode (E), a control electrode (B), and a work electrode (C). A recovery diode (D1; D2) is connected antiparallel to the main flow direction of each main switch (T1). In order to speed up the switch-off process and in particular to reduce the attendant power loss, each main switch (T1) is assigned an electric auxiliary switch (T11; T22), whose work electrode is connected to the control electrode (B) of the associated main switch (T1) and whose reference electrode is connected to the reference electrode (E) of the associated main switch (T1). The capacitor (C11) is disposed between the control electrode of the auxiliary switch (T11; T22) and the work electrode (C) of the associated main switch (T1). A discharge unit (D11) is disposed between the control electrode and the reference electrode of the auxiliary switch in such a way that the capacitor (C11) can be discharged during the transition of the main switch (T1) from the OFF state to the ON state.

Abstract translation: 具有至少一个具有参考电极（E）的电主开关（T1），控制电极（B）和工作电极（C）的电路装置。 恢复二极管（D1; D2）与每个主开关（T1）的主流动方向反平行连接。 为了加快关断过程，特别是为了减少伴随的功率损耗，每个主开关（T1）被分配有辅助开关（T11; T22），其工作电极连接到控制电极（B） 的相关联的主开关（T1），并且其参考电极连接到相关联的主开关（T1）的参考电极（E）。 电容器（C11）设置在辅助开关（T11; T22）的控制电极和相关联的主开关（T1）的工作电极（C）之间。 放电单元（D11）设置在辅助开关的控制电极和参考电极之间，使得电容器（C11）在主开关（T1）从OFF状态转变到ON期间可以被放电 州。

公开(公告)号：US06333664B1

公开(公告)日：2001-12-25

申请号：US09643253

申请日：2000-08-22

Applicant: Dean M. Umberger

Inventor： Dean M. Umberger

IPC: H03K1704

CPC classification number: H03K17/725 ,  H03K17/16 ,  H04M19/02

Abstract: An integrated ringing access switch circuit for telecommunications switching applications that provides improved dV/dt sensitivity at low operating power by using a pilot controlled rectifier, such as an SCR, that conducts at low ringing signal currents and operates to steer a bias current for causing a relatively larger controlled rectifier in parallel therewith to become conductive during higher load current operation. Also included is circuitry for preventing inadvertent turn-on of the SCRs in response to transient signals.

Abstract translation: 一种用于电信交换应用的集成振铃接入开关电路，其通过使用导频控制整流器（例如SCR）在低工作功率下提供改善的dV / dt灵敏度，其在低振铃信号电流下传导并且操作以引导偏置电流以引起 相对较大的受控整流器并联，以在更高负载电流操作期间变为导通。 还包括用于防止响应于瞬态信号的SCR的无意的接通的电路。

公开(公告)号：US06819149B2

公开(公告)日：2004-11-16

申请号：US10457348

申请日：2003-06-10

Applicant: Takaaki Shirasawa ,  Tsuyoshi Takayama

Inventor： Takaaki Shirasawa ,  Tsuyoshi Takayama

IPC: H03K1704

CPC classification number: H03K17/162

Abstract: In a circuit having MOS transistors connected in series, a surge voltage that occurs during off periods is reduced, while suppressing an increase in switching loss at turning off of the MOS transistors. When a first power MOSFET (1) is turned off and then a second power MOSFET (2) is turned on after that according to predetermined timing, the first power MOSFET (1) is temporarily placed in an on state for a predetermined time period synchronized with that predetermined timing. On the other hand, when the second power MOSFET (2) is turned off and then the first power MOSFET (1) is turned on after that according to predetermined timing, the second power MOSFET (2) is temporarily placed in an on state for a predetermined time period synchronized with that predetermined timing.

Abstract translation: 在具有串联连接的MOS晶体管的电路中，在抑制MOS晶体管截止时的开关损耗的增加的同时，减小在关断期间发生的浪涌电压。 当第一功率MOSFET（1）关断，然后根据预定定时接通第二功率MOSFET（2）时，第一功率MOSFET（1）暂时处于接通状态一段预定时间段 与该预定定时。 另一方面，当第二功率MOSFET（2）关断，然后根据预定定时使第一功率MOSFET（1）导通时，第二功率MOSFET（2）暂时置于导通状态 与该预定定时同步的预定时间段。

公开(公告)号：US06614289B1

公开(公告)日：2003-09-02

申请号：US09708336

申请日：2000-11-07

Applicant: Ho-Yuan Yu

Inventor： Ho-Yuan Yu

IPC: H03K1704

CPC classification number: H03K17/04106 ,  H01L27/098 ,  H03K17/04163 ,  H03K17/063 ,  H03K17/567

Abstract: A semiconductor switching device or amplifier combined in parallel with one or more active devices defined as starter devices. A starter device is used to reduce the terminal voltage of a switching device or amplifier to a dc level below about 0.4 volts which will then allow the switching device to easily change between the on or conducting state and the off or non-conducting state. Three different starter devices are utilized. The first being a Bipolar Junction Transistor (BJT), the second a Metal Oxide Silicon Field Effect Transistor (MOSFET), and the third consisting of three normally off JFETs connected serially. Generally, a single starter device is coupled across the terminals of a semiconductor switching device or amplifier, but it is possible and sometimes advantageous to couple two or more starter devices in parallel. In a first case, a symmetrical, normally off or enhancement mode JFET is used as the switch or amplifier. A starter device coupled between source and drain of the JFET will allow operation at dc voltage levels above 0.4 volts. In a second case, an asymmetrical, normally off JFET is used as the switch or amplifier. A starter device coupled between source and drain of the JFET will allow operation at dc voltage levels above 0.4 volts. In a third case, a normally off MESFET is used as the switch or amplifier. A starter device coupled between source and drain of the MESFET will allow operation at dc voltage levels above 0.4 volts.

Abstract translation: 与定义为起动装置的一个或多个有源装置并联组合的半导体开关装置或放大器。 启动器装置用于将开关装置或放大器的端子电压降低到低于约0.4伏特的直流电平，这将允许开关装置容易地在导通或导通状态与断开或非导通状态之间改变。 使用三种不同的起动装置。 第一个是双极结晶体管（BJT），第二个是金属氧化物硅场效应晶体管（MOSFET），第三个由串联连接的三个常闭JFET组成。 通常，单个启动器器件跨越半导体开关器件或放大器的端子耦合，但并联连接两个或多个起动器件是可能的并且有时是有利的。 在第一种情况下，使用对称，常闭或增强型JFET作为开关或放大器。 耦合在JFET的源极和漏极之间的启动器器件将允许在高于0.4伏的直流电压电平下工作。 在第二种情况下，使用非对称的常闭JFET作为开关或放大器。 耦合在JFET的源极和漏极之间的启动器器件将允许在高于0.4伏的直流电压电平下工作。 在第三种情况下，使用常闭MESFET作为开关或放大器。 耦合在MESFET的源极和漏极之间的启动器器件将允许在高于0.4伏的直流电压电平下工作。

公开(公告)号：US06285235B1

公开(公告)日：2001-09-04

申请号：US09266774

申请日：1999-03-12

Applicant: Kosaku Ichikawa ,  Tateo Koyama ,  Hitoshi Matsumura ,  Shinji Sato

Inventor： Kosaku Ichikawa ,  Tateo Koyama ,  Hitoshi Matsumura ,  Shinji Sato

IPC: H03K1704

CPC classification number: H03K17/0406 ,  H02M1/08 ,  H02M1/38 ,  H03K17/04123

Abstract: A gate control circuit for turning on and off an insulated gate semiconductor device having gate, emitter and collector terminals, including a first DC power source coupled to the gate terminal via a first switch and configured to apply a positive voltage to the gate terminal in order to turn on the insulated gate semiconductor device when the first switch is turned on and the second switch is turned off; a second DC power source coupled to the gate terminal via a second switch and configured to apply a negative voltage to the gate terminal in order to turn off the insulated gate semiconductor device when the second switch is turned on and the first switch is turned off; a parallel circuit of a diode and a capacitor coupled in series to the second switch; and a turn off assist circuit configured to produce a negative charge on the capacitor to assist in turning off the insulated gate semiconductor device. In a power converter circuit having a plurality of insulated gate semiconductor devices, equalization of delay times for turning off the insulated gate semiconductor devices is achieved by controlling a charged stored in the capacitor of each gate control circuit based on detected collector-emitter voltages or detected emitter currents.

Abstract translation: 一种用于接通和断开具有栅极，发射极和集电极端子的绝缘栅极半导体器件的栅极控制电路，包括经由第一开关耦合到栅极端子的第一DC电源，并且被配置为按顺序向栅极端子施加正电压 当所述第一开关接通并且所述第二开关断开时，接通所述绝缘栅极半导体器件; 第二直流电源，经由第二开关耦合到所述栅极端子，并且被配置为向所述栅极端子施加负电压，以在所述第二开关导通并且所述第一开关断开时关闭所述绝缘栅极半导体器件; 耦合到第二开关的二极管和电容器的并联电路; 以及关闭辅助电路，其被配置为在所述电容器上产生负电荷以帮助关闭所述绝缘栅极半导体器件。 在具有多个绝缘栅极半导体器件的功率转换器电路中，通过基于检测到的集电极 - 发射极电压控制存储在每个栅极控制电路的电容器中的电荷来实现用于关断绝缘栅极半导体器件的延迟时间的均衡 发射极电流。

公开(公告)号：US06268756B1

公开(公告)日：2001-07-31

申请号：US09649799

申请日：2000-08-29

Applicant: Mehrdad Nayebi ,  Murat Hayri Eskiyerli ,  Phil Shapiro

Inventor： Mehrdad Nayebi ,  Murat Hayri Eskiyerli ,  Phil Shapiro

IPC: H03K1704

CPC classification number: H03K17/615 ,  H03K17/04126

Abstract: A fast high side switch for hard disk drive preamplifiers requires very fast turn on time, very low impedance when the switch is “on” and very high impedance when the switch is turned “off”. Each of the embodiments described provide a low-impedance path between the “Boost Voltage” and “Switch Out” terminals of the hard disk drive preamplifier, i.e., connecting a boost-voltage to the inductor, and as required in such a system, the proposed circuits provide a turn-on time that is much faster than the rise-time of the write current.

公开(公告)号：US06731153B2

公开(公告)日：2004-05-04

申请号：US09963500

申请日：2001-09-27

Applicant: Kanji Otsuka ,  Tamotsu Usami

Inventor： Kanji Otsuka ,  Tamotsu Usami

IPC: H03K1704

CPC classification number: H03K19/01707

Abstract: A CMOS line driver is made up of p- and nMOS transistors. A pMOS varactor is interposed between the source of the pMOS transistor and a power supply, while an nMOS varactor is interposed between the source of the nMOS transistor and ground. The sizes of each of these MOS varactors may be the same as those of the p- or nMOS transistor. Alternatively, each of these MOS varactors may have a channel area twice greater than that of the p- or nMOS transistor. The inverted version of a signal input to the line driver is supplied to the gates of the MOS varactors. In this manner, the MOS transistors, making up the line driver, can switch at a high speed.

Abstract translation: CMOS线路驱动器由p-和nMOS晶体管组成。 pMOS变容二极管介于pMOS晶体管的源极和电源之间，而nMOS变容二极管插在nMOS晶体管的源极和地之间。 这些MOS可变电抗器的尺寸可以与p型或nMOS晶体管的尺寸相同。 或者，这些MOS变容二极管中的每一个可以具有比p型或nMOS晶体管的沟道面积的两倍的沟道面积。 将输入到线路驱动器的信号的反相形式提供给MOS可变电抗器的栅极。 以这种方式，构成线路驱动器的MOS晶体管可以高速切换。

公开(公告)号：US06531909B1

公开(公告)日：2003-03-11

申请号：US09397629

申请日：1999-09-15

Applicant: Karl Edwards

Inventor： Karl Edwards

IPC: H03K1704

CPC classification number: H03K17/04213 ,  H03K17/04126 ,  H03K17/06

Abstract: Techniques and circuits for high speed switching of transistors are provided. These techniques and circuits switch an output device while varying the drive current to the output device in proportion to the output current through the output device. In addition, these techniques and circuits provide a switching circuit with substantially no quiescent currents. This is accomplished by sampling the output current conducted by the output device and using the sample as a signal to drive either the output device fully ON or to switch the output device fully OFF.

Abstract translation: 提供了晶体管高速切换的技术和电路。 这些技术和电路在输出设备的输出电流成比例地改变输出设备的驱动电流的同时切换输出设备。 此外，这些技术和电路提供基本上没有静态电流的开关电路。 这是通过对由输出设备传导的输出电流进行采样并使用样本作为信号来驱动输出设备完全打开或将输出设备完全关断来实现的。

公开(公告)号：US06476661B2

公开(公告)日：2002-11-05

申请号：US09817292

申请日：2001-03-27

Applicant: Stepan Iliasevitch

Inventor： Stepan Iliasevitch

IPC: H03K1704

CPC classification number: G05F3/222

Abstract: A pull-down circuit uses an npn transistor operating at close to saturation and the collector/emitter voltage is used as the pull-down voltage. To keep this within strict limits the npn transistor is connected in circuit with other transistors and resistors as well as a current source that generates a current proportional to absolute temperature. By selecting the values of the resistors and transistor parameters the collector/emitter voltage may be kept stable within a small range over wide temperature variation.

Abstract translation: 下拉电路使用工作在接近饱和的npn晶体管，集电极/发射极电压用作下拉电压。 为了将其保持在严格的限制范围内，npn晶体管与其他晶体管和电阻器以及产生与绝对温度成比例的电流的电流源连接在电路中。 通过选择电阻和晶体管参数的值，集电极/发射极电压可以在较宽的温度变化范围内保持在小范围内。