公开(公告)号：US20100096670A1

公开(公告)日：2010-04-22

申请号：US12642614

申请日：2009-12-18

申请人： Eiichi Hosomi

发明人： Eiichi Hosomi

IPC分类号： H01L27/10 ,  G03C1/00

CPC分类号： H01L27/0203 ,  Y02P80/30

摘要： Methods and devices yielding an improved semiconductor device with interface circuit are disclosed. Configuring a semiconductor with parallel device features reduces process variation (e.g., lithographically-induced process variation or other defects). Embodiments of the present invention provide semiconductor devices with I/O cell device features (e.g., I/O gates or core gates) laid out in parallel. Additionally, embodiments of the present invention can allow patterning devices to be made to more exacting tolerances because some patterning devices may have a higher capability along one axis than another. Embodiments of the present invention also include a semiconductor device having like-functioned I/O cells arranged such that their layouts and rotational orientations with respect to their corresponding core remain constant. Furthermore, disclosed semiconductor devices may include at least one circuit cell having non-parallel features, where the circuit cell is arranged either within the core or within a corresponding interface circuit cell.

摘要翻译： 公开了产生具有接口电路的改进的半导体器件的方法和装置。 配置具有并行器件特征的半导体可以减少工艺变化（例如，光刻引起的工艺变化或其他缺陷）。 本发明的实施例提供具有并联布置的I / O单元装置特征（例如，I / O门或核心门）的半导体器件。 另外，本发明的实施例可以允许将图案形成装置制成更严格的公差，因为一​​些图案形成装置可以沿着一个轴线具有比另一个更高的能力。 本发明的实施例还包括具有相似功能的I / O单元的半导体器件，所述I / O单元被布置成使得它们相对于它们对应的芯的布局和旋转取向保持恒定。 此外，所公开的半导体器件可以包括具有非并行特征的至少一个电路单元，其中电路单元被布置在核心内或在相应的接口电路单元内。

公开(公告)号：US07501698B2

公开(公告)日：2009-03-10

申请号：US10973373

申请日：2004-10-26

申请人： Eiichi Hosomi

发明人： Eiichi Hosomi

IPC分类号： H01L23/12

CPC分类号： H01L23/50 ,  H01L23/49838 ,  H01L2224/16 ,  H01L2924/15311 ,  H01L2924/3011

摘要： Systems and methods for a structure for a power distribution network intended to distribute power from a PCB to a semiconductor device on a package. These improved power distribution networks may reduce current crowding in the BGA balls of a package and may serve to more equitably distribute current through the BGA balls of the package through increasing the impedance of the package or decreasing the impedance of the PCB to which the package is coupled. These systems and methods may increase the impedance of the package through various arrangements of the coupling between BGA balls and planes of the package. By the same token, these systems and methods may decrease the impedance of the PCB coupled to the package by arrangement of the coupling between the PCB and the BGA balls of the package.

摘要翻译： 用于配电网络的结构的系统和方法，用于将功率从PCB分配到封装上的半导体器件。 这些改进的配电网络可以减少封装的BGA球中的电流拥挤，并且可以用于通过增加封装的阻抗或减小封装的PCB的阻抗来更均匀地分配电流通过封装的BGA球的电流 耦合。 这些系统和方法可以通过BGA球和包装平面之间的耦合的各种布置来增加封装的阻抗。 同样地，这些系统和方法可以通过布置PCB和封装的BGA球之间的耦合来减小耦合到封装的PCB的阻抗。

公开(公告)号：US20050051810A1

公开(公告)日：2005-03-10

申请号：US10968890

申请日：2004-10-21

申请人： Hiroshi Funakura ,  Eiichi Hosomi ,  Yasuhiro Koshio ,  Tetsuya Nagaoka ,  Junya Nagano ,  Mitsuru Oida ,  Masatoshi Fukuda ,  Atsushi Kurosu ,  Kaoru Kawai ,  Osamu Yamagata

发明人： Hiroshi Funakura ,  Eiichi Hosomi ,  Yasuhiro Koshio ,  Tetsuya Nagaoka ,  Junya Nagano ,  Mitsuru Oida ,  Masatoshi Fukuda ,  Atsushi Kurosu ,  Kaoru Kawai ,  Osamu Yamagata

IPC分类号： H01L23/29 ,  H01L21/56 ,  H01L23/12 ,  H01L23/28 ,  H01L23/31 ,  H01L23/498 ,  H01L29/768

CPC分类号： H01L23/49894 ,  H01L23/3121 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.

摘要翻译： 半导体封装具有（a）封装基座，（b）形成在封装基座上并用于将半导体封装连接到另一器件的封装端子，（c）形成在封装基座上并电连接到封装端子的布线层 ，（d）安装在封装基板上并电连接到布线层的半导体芯片，（e）在树脂模具和布线层之间以及封装基底和树脂模具之间形成的低弹性树脂层，和 f）树脂模具密封封装基座，布线层，半导体芯片和低弹性树脂层。

公开(公告)号：US06768206B2

公开(公告)日：2004-07-27

申请号：US10141685

申请日：2002-05-07

申请人： Eiichi Hosomi

发明人： Eiichi Hosomi

IPC分类号： H01L2348

CPC分类号： H01L23/49838 ,  H01L23/49827 ,  H01L2224/16 ,  H01L2924/01078 ,  H01L2924/15311

摘要： An exemplary embodiment of the present invention described and shown in the specification and drawings is a substrate that has lattice points and interstitial points. The substrate includes a surface, a plurality pads located on the surface at interstitial points, and a plurality of vias located in the substrate only at lattice points.

摘要翻译： 在说明书和附图中描述和示出的本发明的示例性实施例是具有格点和间隙点的基底。 衬底包括表面，位于间隙点的表面上的多个衬垫以及仅在格子点处位于衬底中的多个通孔。

公开(公告)号：US06551854B2

公开(公告)日：2003-04-22

申请号：US09813160

申请日：2001-03-21

申请人： Eiichi Hosomi ,  Yasuhiro Koshio

发明人： Eiichi Hosomi ,  Yasuhiro Koshio

IPC分类号： H01L2144

CPC分类号： H01L24/13 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/05624 ,  H01L2224/1134 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/13144 ,  H01L2224/81801 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01041 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2924/00014

摘要： A semiconductor device includes a bonding layer which consists of an intermetallic compound and is positioned between a first electrode and a bump electrode. The bump electrode is mainly made of Au. The intermetallic compound of the bonding layer consist of Au of the bump electrode and a low melting metal.

摘要翻译： 半导体器件包括由金属间化合物组成并且位于第一电极和凸块电极之间的接合层。 凸块电极主要由Au制成。 接合层的金属间化合物由凸起电极的Au和低熔点金属组成。

公开(公告)号：US06469373B2

公开(公告)日：2002-10-22

申请号：US09854559

申请日：2001-05-15

申请人： Hiroshi Funakura ,  Eiichi Hosomi

发明人： Hiroshi Funakura ,  Eiichi Hosomi

IPC分类号： H01L2302

CPC分类号： H01L23/3121 ,  H01L21/563 ,  H01L24/45 ,  H01L24/48 ,  H01L24/97 ,  H01L2224/16 ,  H01L2224/45147 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2924/00014 ,  H01L2924/00012

摘要： In a semiconductor apparatus comprising a semiconductor chip, a wiring substrate having the semiconductor chip mounted thereon, an under-fill resin sheet interposed between the semiconductor chip and the wiring substrate, and a resin sealing body for sealing the semiconductor chip, the under-fill resin sheet and the wiring substrate, the under-fill resin sheet is greater than the semiconductor chip in size, and its end is exposed from at least one side face of the resin sealing body. Since an end of the under-fill resin sheet is exposed from at least one side face of the resin sealing body, then the water contained in the under-fill resin sheet escapes from an exposed end of the under-fill resin sheet to the outside of the resin sealing body, thus making it possible to improve re-flow resistance of the semiconductor apparatus.

摘要翻译： 在包括半导体芯片的半导体装置中，安装有半导体芯片的布线基板，插入在半导体芯片和布线基板之间的未填充树脂片，以及用于密封半导体芯片的树脂密封体， 树脂片和布线基板，未填充树脂片的尺寸大于半导体芯片，其端部从树脂密封体的至少一个侧面露出。 由于填充不足的树脂片的端部从树脂密封体的至少一个侧面露出，所以填充后的树脂片中所含的水从填充后的树脂片的露出端向外部排出到外部 的树脂密封体，从而可以提高半导体装置的再流动阻力。

公开(公告)号：US06376907B1

公开(公告)日：2002-04-23

申请号：US09201866

申请日：1998-11-30

申请人： Eiji Takano ,  Eiichi Hosomi ,  Chiaki Takubo

发明人： Eiji Takano ,  Eiichi Hosomi ,  Chiaki Takubo

IPC分类号： H01L2312

CPC分类号： H01L23/04 ,  H01L23/10 ,  H01L2224/16 ,  H01L2224/16225 ,  H01L2224/32245 ,  H01L2224/73204 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16151 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2224/0401

摘要： A semiconductor device with a BGA package includes a substrate made of a resin and having one side on which a number of solder ball terminals are formed and the other side on which a chip mounting portion electrically connected to the solder ball terminals is formed, and a cover plate made of a metal and attached to a semiconductor chip so as to cover and come into contact with it under a condition where the semiconductor chip is connected to the resin substrate by a flip-chip process. The cover plate includes a base brought into contact with the semiconductor chip and a peripheral portion formed with a plurality of bonding portions where the cover plate is bonded to the substrate. The bonding portions are discontinuous to each other.

摘要翻译： 具有BGA封装的半导体器件包括由树脂制成的衬底，其一侧形成有多个焊球端子，另一侧形成有与焊球端子电连接的芯片安装部， 由金属构成的盖板，并且在半导体芯片通过倒装芯片工艺连接到树脂基板的状态下被覆盖并与其接触。 盖板包括与半导体芯片接触的基座和形成有多个接合部分的边缘部分，其中盖板结合到基板。 接合部彼此不连续。

公开(公告)号：US6061466A

公开(公告)日：2000-05-09

申请号：US773054

申请日：1996-12-24

申请人： Chiaki Takubo ,  Eiichi Hosomi ,  Hiroshi Tazawa ,  Koji Shibasaki

发明人： Chiaki Takubo ,  Eiichi Hosomi ,  Hiroshi Tazawa ,  Koji Shibasaki

IPC分类号： G01B11/02 ,  G01N21/88 ,  G01R31/04 ,  G01R31/309 ,  G06T7/00 ,  H01L21/60 ,  H01L21/66 ,  G06K9/00

CPC分类号： G06T7/0004 ,  G01N21/88 ,  G01R31/046 ,  G01R31/309 ,  G06T2207/30148

摘要： Disclosed is an apparatus and method for inspecting a connection state of a lead electrode to a bump after TAB (tape automated bonding). An LSI chip is immobilized on a stage. A flexible lead is held by a holding portion and connected to a bump. Above the chip, a CCD camera is provided. The stage is controlled to move up and down by a moving control mechanism. Each of the lead/bump connection states immediately after ILB (Inner lead bonding) is taken in the form of image data and defined as a first image data. A second image data of the lead/bump connection state is taken after the bump and lead are moved to different positions by moving the stage in order to change the position of the chip by means of the moving control mechanism. Whether or not the lead is duly connected to the bump is determined by the comparison of the first and second image data.

摘要翻译： 公开了一种用于在TAB（带自动接合）之后检查引线电极与凸块的连接状态的装置和方法。 将LSI芯片固定在台上。 柔性引线由保持部分保持并连接到凸块。 在芯片之上，提供了一个CCD相机。 通过移动控制机构控制舞台上下移动。 在ILB（内引线接合）之后紧接着的引导/碰撞连接状态以图像数据的形式获取并被定义为第一图像数据。 引导/凸起连接状态的第二图像数据是在通过移动台之后将凸起和引线移动到不同位置之后进行的，以通过移动控制机构改变芯片的位置。 通过第一和第二图像数据的比较来确定引线是否正确连接到凸块。

公开(公告)号：US20060286754A1

公开(公告)日：2006-12-21

申请号：US11154150

申请日：2005-06-16

申请人： Eiichi Hosomi

发明人： Eiichi Hosomi

IPC分类号： H01L21/336

CPC分类号： H01L27/0203 ,  Y02P80/30

摘要： Methods and devices yielding an improved semiconductor device with interface circuit are disclosed. Configuring a semiconductor with parallel device features reduces process variation (e.g., lithographically-induced process variation or other defects). Embodiments of the present invention provide semiconductor devices with I/O cell device features (e.g., I/O gates or core gates) laid out in parallel. Additionally, embodiments of the present invention can allow patterning devices to be made to more exacting tolerances because some patterning devices may have a higher capability along one axis than another. Embodiments of the present invention also include a semiconductor device having like-functioned I/O cells arranged such that their layouts and rotational orientations with respect to their corresponding core remain constant. Furthermore, disclosed semiconductor devices may include at least one circuit cell having non-parallel features, where the circuit cell is arranged either within the core or within a corresponding interface circuit cell.

摘要翻译： 公开了产生具有接口电路的改进的半导体器件的方法和装置。 配置具有并行器件特征的半导体可以减少工艺变化（例如，光刻引起的工艺变化或其他缺陷）。 本发明的实施例提供具有并联布置的I / O单元装置特征（例如，I / O门或核心门）的半导体器件。 另外，本发明的实施例可以允许将图案形成装置制成更严格的公差，因为一​​些图案形成装置可以沿着一个轴线具有比另一个更高的能力。 本发明的实施例还包括具有相似功能的I / O单元的半导体器件，所述I / O单元被布置成使得它们相对于它们对应的芯的布局和旋转取向保持恒定。 此外，所公开的半导体器件可以包括具有非并行特征的至少一个电路单元，其中电路单元被布置在核心内或在相应的接口电路单元内。

公开(公告)号：US20060237829A1

公开(公告)日：2006-10-26

申请号：US11114808

申请日：2005-04-26

申请人： Eiichi Hosomi

发明人： Eiichi Hosomi

IPC分类号： H01L23/02

CPC分类号： H01L23/467 ,  H01L23/3675 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： Systems and methods for a structure for semiconductor packages where the effects that features on the package substrate have on the impedance of signal traces within the semiconductor package is substantially reduced. These systems and methods may allow a feature, or multiple features, to be placed anywhere on the semiconductor package while still minimizing the effect of these features on the impedance of signal traces within the package substrate of the semiconductor package that are beneath these features. In particular, these systems and methods may be useful in a semiconductor package with an air vent, such that the placement of an air vent or air vents in the semiconductor package does not affect signal traces beneath the air vent. Thus, a design rule applicable to signal traces in the remainder of that region may be applied to any signal traces that happen to exist beneath the air vent.

摘要翻译： 用于半导体封装的结构的系统和方法，其中封装衬底上的特征的影响对半导体封装内的信号迹线的阻抗基本上降低。 这些系统和方法可以允许将特征或多个特征放置在半导体封装上的任何位置，同时仍然最小化这些特征对半导体封装的封装衬底中位于这些特征之下的信号迹线的阻抗的影响。 特别地，这些系统和方法可能在具有排气口的半导体封装中是有用的，使得排气孔或通气孔在半导体封装中的放置不会影响通气孔下方的信号迹线。 因此，适用于该区域的其余部分中的信号迹线的设计规则可以应用于恰好存在于通风口下方的任何信号迹线。