公开(公告)号：US20050051810A1

公开(公告)日：2005-03-10

申请号：US10968890

申请日：2004-10-21

Applicant: Hiroshi Funakura ,  Eiichi Hosomi ,  Yasuhiro Koshio ,  Tetsuya Nagaoka ,  Junya Nagano ,  Mitsuru Oida ,  Masatoshi Fukuda ,  Atsushi Kurosu ,  Kaoru Kawai ,  Osamu Yamagata

Inventor： Hiroshi Funakura ,  Eiichi Hosomi ,  Yasuhiro Koshio ,  Tetsuya Nagaoka ,  Junya Nagano ,  Mitsuru Oida ,  Masatoshi Fukuda ,  Atsushi Kurosu ,  Kaoru Kawai ,  Osamu Yamagata

IPC: H01L23/29 ,  H01L21/56 ,  H01L23/12 ,  H01L23/28 ,  H01L23/31 ,  H01L23/498 ,  H01L29/768

CPC classification number: H01L23/49894 ,  H01L23/3121 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.

Abstract translation: 半导体封装具有（a）封装基座，（b）形成在封装基座上并用于将半导体封装连接到另一器件的封装端子，（c）形成在封装基座上并电连接到封装端子的布线层 ，（d）安装在封装基板上并电连接到布线层的半导体芯片，（e）在树脂模具和布线层之间以及封装基底和树脂模具之间形成的低弹性树脂层，和 f）树脂模具密封封装基座，布线层，半导体芯片和低弹性树脂层。

公开(公告)号：US06960494B2

公开(公告)日：2005-11-01

申请号：US10968890

申请日：2004-10-21

Applicant: Hiroshi Funakura ,  Eiichi Hosomi ,  Yasuhiro Koshio ,  Tetsuya Nagaoka ,  Junya Nagano ,  Mitsuru Oida ,  Masatoshi Fukuda ,  Atsushi Kurosu ,  Kaoru Kawai ,  Osamu Yamagata

Inventor： Hiroshi Funakura ,  Eiichi Hosomi ,  Yasuhiro Koshio ,  Tetsuya Nagaoka ,  Junya Nagano ,  Mitsuru Oida ,  Masatoshi Fukuda ,  Atsushi Kurosu ,  Kaoru Kawai ,  Osamu Yamagata

IPC: H01L23/29 ,  H01L21/56 ,  H01L23/12 ,  H01L23/28 ,  H01L23/31 ,  H01L23/498 ,  H01L21/44

CPC classification number: H01L23/49894 ,  H01L23/3121 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.

公开(公告)号：US06836012B2

公开(公告)日：2004-12-28

申请号：US10108363

申请日：2002-03-29

Applicant: Hiroshi Funakura ,  Eiichi Hosomi ,  Yasuhiro Koshio ,  Tetsuya Nagaoka ,  Junya Nagano ,  Mitsuru Oida ,  Masatoshi Fukuda ,  Atsushi Kurosu ,  Kaoru Kawai ,  Osamu Yamagata

Inventor： Hiroshi Funakura ,  Eiichi Hosomi ,  Yasuhiro Koshio ,  Tetsuya Nagaoka ,  Junya Nagano ,  Mitsuru Oida ,  Masatoshi Fukuda ,  Atsushi Kurosu ,  Kaoru Kawai ,  Osamu Yamagata

IPC: H01L2314

CPC classification number: H01L23/49894 ,  H01L23/3121 ,  H01L24/48 ,  H01L2224/16225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48228 ,  H01L2924/00014 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor package has (a) a package base, (b) package terminals formed on the package base and used to connect the semiconductor package to another device, (c) a wiring layer formed on the package base and electrically connected to the package terminals, (d) a semiconductor chip mounted on the package base and electrically connected to the wiring layer, (e) a low-elasticity resin layer formed between a resin mold and the wiring layer and between the package base and the resin mold, and (f) the resin mold sealing the package base, the wiring layer, the semiconductor chip, and the low-elasticity resin layer.

Abstract translation: 半导体封装具有（a）封装基座，（b）形成在封装基座上并用于将半导体封装连接到另一器件的封装端子，（c）形成在封装基座上并电连接到封装端子的布线层 ，（d）安装在封装基板上并电连接到布线层的半导体芯片，（e）在树脂模具和布线层之间以及封装基底和树脂模具之间形成的低弹性树脂层，和 f）树脂模具密封封装基座，布线层，半导体芯片和低弹性树脂层。

公开(公告)号：US5715147A

公开(公告)日：1998-02-03

申请号：US641222

申请日：1996-04-30

Applicant: Junya Nagano

Inventor： Junya Nagano

IPC: H01L23/52 ,  H01L23/495 ,  H01L25/04 ,  H01L25/065 ,  H01L25/18 ,  H05K5/02

CPC classification number: H01L23/49575 ,  H01L23/49531 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  Y10T29/49121 ,  Y10T29/4913

Abstract: A semiconductor device having an interconnecting circuit board includes an island formed in a predetermined plane, a semiconductor chip disposed on the island and having a plurality of electrically connecting electrode pads, an interconnecting circuit board disposed on the semiconductor chip and having an electrically conductive pattern, a plurality of inner leads disposed around the island, a first electrically connecting wire connecting the electrically conductive pattern and one of the plurality of electrically connecting electrode pads, and a second electrically connecting wire connecting the electrically conductive pattern and one of the inner leads.

公开(公告)号：US5613295A

公开(公告)日：1997-03-25

申请号：US460734

申请日：1995-06-02

Applicant: Junya Nagano

Inventor： Junya Nagano

IPC: H01L23/52 ,  H01L23/495 ,  H01L25/04 ,  H01L25/065 ,  H01L25/18 ,  H01R43/00

CPC classification number: H01L23/49575 ,  H01L23/49531 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  Y10T29/49121 ,  Y10T29/4913

Abstract: A semiconductor device having an interconnecting circuit board includes an island formed in a predetermined plane, a semiconductor chip disposed on the island and having a plurality of electrically connecting electrode pads, an interconnecting circuit board disposed on the semiconductor chip and having an electrically conductive pattern, a plurality of inner leads disposed around the island, a first electrically connecting wire connecting the electrically conductive pattern and one of the plurality of electrically connecting electrode pads, and a second electrically connecting wire connecting the electrically conductive pattern and one of the inner leads.

Abstract translation: 具有互连电路板的半导体器件包括形成在预定平面中的岛，设置在岛上的半导体芯片，并且具有多个电连接电极焊盘，布置在半导体芯片上并具有导电图案的互连电路板， 设置在所述岛周围的多个内引线，连接所述导电图案和所述多个电连接电极焊盘中的一个的第一电连接线，以及连接所述导电图案和所述内引线中的一个的第二电连接线。

公开(公告)号：US5646830A

公开(公告)日：1997-07-08

申请号：US460792

申请日：1995-06-02

Applicant: Junya Nagano

Inventor： Junya Nagano

IPC: H01L23/52 ,  H01L23/495 ,  H01L25/04 ,  H01L25/065 ,  H01L25/18 ,  H05K5/02 ,  H01L23/12

CPC classification number: H01L23/49575 ,  H01L23/49531 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  Y10T29/49121 ,  Y10T29/4913

Abstract: A semiconductor device having an interconnecting circuit board includes an island formed in a predetermined plane, a semiconductor chip disposed on the island and having a plurality of electrically connecting electrode pads, an interconnecting circuit board disposed on the semiconductor chip and having an electrically conductive pattern, a plurality of inner leads disposed around the island, a first electrically connecting wire connecting the electrically conductive pattern and one of the plurality of electrically connecting electrode pads, and a second electrically connecting wire connecting the electrically conductive pattern and one of the inner leads.

Abstract translation: 具有互连电路板的半导体器件包括形成在预定平面中的岛，设置在岛上的半导体芯片，并且具有多个电连接电极焊盘，布置在半导体芯片上并具有导电图案的互连电路板， 设置在所述岛周围的多个内引线，连接所述导电图案和所述多个电连接电极焊盘中的一个的第一电连接线，以及连接所述导电图案和所述内引线之一的第二电连接线。

公开(公告)号：US5552966A

公开(公告)日：1996-09-03

申请号：US460559

申请日：1995-06-02

Applicant: Junya Nagano

Inventor： Junya Nagano

IPC: H01L23/52 ,  H01L23/495 ,  H01L25/04 ,  H01L25/065 ,  H01L25/18 ,  H05K5/02

CPC classification number: H01L23/49575 ,  H01L23/49531 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  Y10T29/49121 ,  Y10T29/4913

Abstract: A semiconductor device having an interconnecting circuit board includes an island formed in a predetermined plane, a semiconductor chip disposed on the island and having a plurality of electrically connecting electrode pads, an interconnecting circuit board disposed on the semiconductor chip and having an electrically conductive pattern, a plurality of inner leads disposed around the island, a first electrically connecting wire connecting the electrically conductive pattern and one of the plurality of electrically connecting electrode pads, and a second electrically connecting wire connecting the electrically conductive pattern and one of the inner leads.

Abstract translation: 具有互连电路板的半导体器件包括形成在预定平面中的岛，设置在岛上的半导体芯片，并且具有多个电连接电极焊盘，布置在半导体芯片上并具有导电图案的互连电路板， 设置在所述岛周围的多个内引线，连接所述导电图案和所述多个电连接电极焊盘中的一个的第一电连接线，以及连接所述导电图案和所述内引线中的一个的第二电连接线。

公开(公告)号：US5473514A

公开(公告)日：1995-12-05

申请号：US253589

申请日：1994-06-03

Applicant: Junya Nagano

Inventor： Junya Nagano

IPC: H01L23/52 ,  H01L23/495 ,  H01L25/04 ,  H01L25/065 ,  H01L25/18 ,  H05K5/02 ,  H01L23/12

CPC classification number: H01L23/49575 ,  H01L23/49531 ,  H01L24/49 ,  H01L25/0655 ,  H01L2224/05554 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48145 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/4911 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/1305 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19107 ,  Y10T29/49121 ,  Y10T29/4913

Abstract: A semiconductor device having an interconnecting circuit board includes an island formed in a predetermined plane, a semiconductor chip disposed on the island and having a plurality of electrically connecting electrode pads, an interconnecting circuit board disposed on the semiconductor chip and having an electrically conductive pattern, a plurality of inner leads disposed around the island, a first electrically connecting wire connecting the electrically conductive pattern and one of the plurality of electrically connecting electrode pads, and a second electrically connecting wire connecting the electrically conductive pattern and one of the inner leads.

Abstract translation: 具有互连电路板的半导体器件包括形成在预定平面中的岛，设置在岛上的半导体芯片，并且具有多个电连接电极焊盘，布置在半导体芯片上并具有导电图案的互连电路板， 设置在所述岛周围的多个内引线，连接所述导电图案和所述多个电连接电极焊盘中的一个的第一电连接线，以及连接所述导电图案和所述内引线之一的第二电连接线。